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參數(shù)資料

型號(hào)：	DS2153Q-A7+T&R
廠商：	Maxim Integrated Products
文件頁數(shù)：	30/60頁
文件大?。?/td>	0K
描述：	IC TXRX E1 1-CHIP 5V 44-PLCC
產(chǎn)品培訓(xùn)模塊：	Lead (SnPb) Finish for COTS Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝：	500
功能：	單芯片收發(fā)器
接口：	E1
電路數(shù)：	1
電源電壓：	4.75 V ~ 5.25 V
電流 - 電源：	65mA
工作溫度：	0°C ~ 70°C
安裝類型：	表面貼裝
封裝/外殼：	44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝：	44-PLCC（16.59x16.59）
包裝：	帶卷 (TR)

DS2153Q

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12 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION

The DS2153Q provides for access to both the Additional (Sa) and International (Si) bits. On the receive

side, the RAF and RNAF registers will always report the data as it received in the Additional and

International bit locations. The RAF and RNAF registers are updated with the setting of the Receive

Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the

RAF and RNAF registers. It has 250

s to retrieve the data before it is lost.

On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit

Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the

TAF and TNAF registers. It has 250

s to update the data or else the old data will be retransmitted. Data

in the Si bit position will be overwritten if either the DS2153Q is programmed: (1) to source the Si bits

from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. Data in the Sa

bit position will be overwritten if any of the TCR2.3 to TCR2.7 bits are set to 1. See the register

descriptions for TCR1 and TCR2 and the Transmit Data Flow diagram in Section 14 for more details.

RAF: RECEIVE ALIGN FRAME REGISTER (Address = 2F Hex)

(MSB)

(LSB)

SYMBOL

POSITION

NAME AND DESCRIPTION

RAF.7

International Bit.

RAF.6