參數(shù)資料
型號(hào): DS2153Q-A7+T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 8/60頁(yè)
文件大?。?/td> 0K
描述: IC TXRX E1 1-CHIP 5V 44-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
功能: 單芯片收發(fā)器
接口: E1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 65mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
DS2153Q
16 of 60
CCR3: COMMON CONTROL REGISTER 3 (Address = 1B Hex)
(MSB)
(LSB)
TESE
TCBFS
TIRFS
ESR
LIRST
TSCLKM
SYMBOL
POSITION
NAME AND DESCRIPTION
TESE
CCR3.7
Transmit Elastic Store Enable.
0 = elastic store is disabled
1 = elastic store is enabled
TCBFS
CCR3.6
Transmit Channel Blocking Registers (TCBR) Function
Select.
0 = TCBRs define the operation of the TCHBLK output pin
1 = TCBRs define which signaling bits are to be inserted
TIRFS
CCR3.5
Transmit Idle Registers (TIR) Function Select.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER
ESR
CCR3.4
Elastic Stores Reset. Setting this bit from a 1 to a 0 will force
the elastic stores to a known depth. Should be toggled after
SYSCLK has been applied and is stable. Must be set and cleared
again for a subsequent reset. Do not leave this bit set high.
LIRST
CCR3.3
Line Interface Reset. Setting this bit from a 0 to a 1 will initiate
an internal reset that affects the slicer, AGC, clock recovery state
machine, and jitter attenuator. Normally this bit is only toggled
on power-up. Must be cleared and set again for a subsequent
reset.
CCR3.2
Not Assigned. Should be set to 0 when written.
TSCLKM
CCR3.1
Transmit Backplane Clock Select. Must be set like RCR2.2.
0 = 1.544MHz
1 = 2.048MHz
CCR3.0
Not Assigned. Should be set to 0 when written.
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