參數(shù)資料
型號(hào)： DS21Q50N
英文描述： Telecommunication IC
中文描述： 通信集成電路
文件頁(yè)數(shù)： 2/99頁(yè)
文件大?。?/td> 325K
代理商： DS21Q50N
DS21Q50
Page 2 of 99
TABLE OF CONTENTS
FEATURES.........................................................................................................................1
ORDERING INFORMATION.........................................................................................1
DESCRIPTION..................................................................................................................1
1. LIST OF FIGURES .....................................................................................................4
2. LIST OF TABLES .......................................................................................................5
3. INTRODUCTION.......................................................................................................6
4. FUNCTIONAL DESCRIPTION ................................................................................6
4.1
DOCUMENT REVISION HISTORY.....................................................................7
5. PIN DESCRIPTION....................................................................................................9
5.1
PIN FUNCTION DESCRIPTION........................................................................15
5.1.1
System (Backplane) Interface Pins................................................................15
5.1.2
Alternate Jitter Attenuator............................................................................16
5.1.3
Clock Synthesizer...........................................................................................16
5.1.4
Parallel Port Control Pins.............................................................................17
5.1.5
Serial Port Control Pins................................................................................18
5.1.6
Line Interface Pins.........................................................................................19
5.1.7
Supply Pins.....................................................................................................20
6. HOST INTERFACE PORT......................................................................................21
6.1
6.2
6.3
P
ARALLEL
P
ORT
O
PERATION
.................................................................................21
S
ERIAL
P
ORT
O
PERATION
......................................................................................21
REGISTER MAP...................................................................................................24
7. CONTROL, ID, AND TEST REGISTERS .............................................................25
7.1
7.2
7.3
7.4
7.5
P
OWER
–U
P
S
EQUENCE
...........................................................................................26
F
RAMER
L
OOPBACK
...............................................................................................29
A
UTOMATIC
A
LARM
G
ENERATION
........................................................................31
R
EMOTE
L
OOPBACK
...............................................................................................32
L
OCAL
L
OOPBACK
.................................................................................................32
8. STATUS AND INFORMATION REGISTERS......................................................35
8.1
CRC4 S
YNC
C
OUNTER
...........................................................................................37
9. ERROR COUNT REGISTERS................................................................................43
9.1
9.2
9.3
9.4
BPV
OR
C
ODE
V
IOLATION
C
OUNTER
.....................................................................43
CRC4 E
RROR
C
OUNTER
.........................................................................................44
E–B
IT
/ PRBS B
IT
E
RROR
C
OUNTER
......................................................................45
FAS E
RROR
C
OUNTER
...........................................................................................46
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