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參數(shù)資料
| 型號(hào)： | DS21Q50N |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 6/99頁(yè) |
| 文件大?。?/td> | 325K |
| 代理商： | DS21Q50N |
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DS21Q50
Page 6 of 99
3. INTRODUCTION
The DS21Q50 is optimized for high-density termination of E1 lines. Two significant features are included for this
type of application, Interleave Bus Option and a System Clock Synthesizer feature. The Interleave Bus Option
allows up to 8 E1 data streams to be multiplexed onto a single high-speed PCM bus without additional external
logic. The System Clock Synthesizer feature allows any of the E1 lines to be selected as the master source of
clock for the system and for all the transmitters. This is also accomplished without the need of external logic.
Each of the 4 transceivers has a clock and data jitter attenuator that can be assigned to either the transmit or
receive path. In addition there is a single, undedicated clock jitter attenuator that can be hardware configured as
the user needs. Each transceiver also contains a PRBS pattern generator and detector. Figure 21-1 shows a
simplified typical application which terminates 8 E1 lines (transmit and receive pairs) and combines the data into a
single 16.384MHz PCM bus. The 16.384MHz system clock is derived and phased locked to one of the 8 E1
lines. On the receive side of each port, an elastic store provides logical management of any slip conditions due to
the asynchronous relationship of the 8 E1 lines. In this application all 8 transmitters are timed to the selected E1
line.
4. FUNCTIONAL DESCRIPTION
The analog AMI/HDB3 waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of the
DS21Q50. The device recovers clock and data from the analog signal and passes it through the jitter attenuation
mux to the receive framer where the digital serial stream is analyzed to locate the framing/multi-frame pattern. The
DS21Q50 contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur
in transmission. The device has a usable receive sensitivity of 0 dB to –43 dB which allows the device to operate
on cables over 2km in length. The receive framer locates FAS frame and CRC and CAS multiframe boundaries
as well as detects incoming alarms including, carrier loss, loss of synchronization, AIS and Remote Alarm. If
needed, the receive elastic store can be enabled in order to absorb the phase and frequency differences between
the recovered E1 data stream and an asynchronous backplane clock which is provided at the SYSCLK input.
The clock applied at the SYSCLK input can be either a 2.048/4.096/8.192 or 16.384MHz clock. The transmit
framer is independent from the receive in both the clock requirements and characteristics. The transmit formatter
will provide the necessary frame/multiframe data overhead for E1 transmission.
Reader’s Note:
This data sheet assumes a particular nomenclature of the E1 operating environment. In each
125 us frame, there are 32 eight–bit timeslots numbered 0 to 31. Timeslot 0 is transmitted first and received first.
These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is identical to
channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or channel) is made up of eight bits
which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is
transmitted last. The term “l(fā)ocked” is used to refer to two clock signals that are phase or frequency locked or
derived from a common clock (i.e., a 8.192MHz clock may be locked to a 2.048MHz clock if they share the
same 8KHz component). Throughout this data sheet, the following abbreviations will be used:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21Q55DK | Quad T1/E1/J1 Transceiver Design Kit Daughter Card |
| DS21Q55 | Quad T1/E1/J1 Transceiver |
| DS21Q55N | Quad T1/E1/J1 Transceiver |
| DS21S07A | SCSI Terminator |
| DS21S07AE | Terminator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q55 | 功能描述:IC TXRX QUAD T1/E1/J1 SCT 256BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| DS21Q552 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V Quad T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q552+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V Quad T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q552B | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS21Q552BN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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