參數(shù)資料
型號(hào)： DS21Q50N
英文描述： Telecommunication IC
中文描述： 通信集成電路
文件頁(yè)數(shù)： 21/99頁(yè)
文件大小： 325K
代理商： DS21Q50N
DS21Q50
Page 21 of 99
6. HOST INTERFACE PORT
The DS21Q50 is controlled via either a non–multiplexed bus, a multiplexed bus or serial interface bus by an
external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing
configurations. See Table 6-1 for a description of the bus configurations. All Motorola bus signals are listed in
parenthesis (). See the timing diagrams in the A.C. Electrical Characteristics in Section 22 for more details.
Table 6-1 BUS MODE SELECT
PBTS
BTS1
BTS0
0
0
0
0
0
1
1
0
0
1
0
1
Motorola Non-Multiplexed
X
1
0
X
1
1
TEST (Outputs High Z)
6.1 PARALLEL PORT OPERATION
When using the parallel interface on the DS21Q50 (BTS1 = 0) the user has the option for either multiplexed bus
operation (BTS1 = 0, BTS0 = 0) or non-multiplexed bus operation (BTS1 = 0, BTS0 = 1). The DS21Q50 can
operate with either Intel or Motorola bus timing configurations. If the PBTS pin is tied low, Intel timing will be
selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parenthesis (). See
the timing diagrams in section 24 for more details.
6.2 SERIAL PORT OPERATION
Setting BTS1 pin = 1 and the BTS0 pin = 0 enables the serial bus interface on the DS21Q50. Port read/write
timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host.
See Section 24 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 6-1,
Figure 6-2, Figure 6-3, and Figure 6-4 for more details.
Reading or writing to the internal registers requires writing one address/command byte prior to transferring
register data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1)
or a write (0). The next 5 bits identify the register address. The next bit is reserved and must be set to 0 for
proper operation. The last bit (MSB) of the address/command byte enables the burst mode when set to 1. The
burst mode causes all registers to be consecutively written or read.
All data transfers are initiated by driving the CS* input low. When Input Clock-Edge Select (ICES) is low, input
data is latched on the rising edge of SCLK and when ICES is high, input data is latched on the falling edge of
SCLK. When Output Clock-Edge Select (OCES) is low, data is output on the falling edge of SCLK and when
OCES is high, data is output on the rising edge of SCLK. Data is held until the next falling or rising edge. All
data transfers are terminated if the CS* input transitions high. Port control logic is disabled and SDO is tri-stated
when CS* is high.
Figure 6-1 SERIAL PORT OPERATION MODE 1
ICES = 1 (sample SDI on the falling edge of SCLK)
OCES = 1 (update SDO on rising edge of SCLK)
Parallel Port Mode
Intel Multiplexed
Intel Non-Multiplexed
Motorola Multiplexed
Serial
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