參數(shù)資料
型號: DS21Q50N
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 26/99頁
文件大小: 325K
代理商: DS21Q50N
DS21Q50
Page 26 of 99
7.1 POWER–UP SEQUENCE
On power–up, after the supplies are stable the DS21Q50 should be configured for operation by writing to all of
the internal registers (this includes setting the Test Registers to 00h) since the contents of the internal registers
cannot be predicted on power–up. The LIRST (CCR5.4) should be toggled from zero to one to reset the line
interface circuitry (it will take the device about 40ms to recover from the LIRST bit being toggled). Finally, after
the SYSCLK input is stable, the ESR bits (CCR4.5 & CCR4.6) should be toggled from a zero to a one (this
step can be skipped if the elastic store is disabled).
Register Name:
RCR
Register Description:
RECEIVE CONTROL REGISTER
Register Address:
10 Hex
Bit #
7
6
5
4
SYM
RSMF
RSM
RSIO
RESE
3
-
2
1
0
FRC
SYNCE RESYN
C
SYMBOL
RSMF
BIT NAME AND DESCRIPTION
7
RSYNC Multiframe Function.
Only used if the RSYNC pin is
programmed in the multiframe mode (RCR.6=1).
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC4 multiframe boundaries
6
RSYNC Mode Select.
0 = frame mode (see the timing in Section 22.1)
1 = multiframe mode (see the timing in Section 22.1)
5
RSYNC I/O Select.
(Note: this bit must be set to zero when RCR
.4=0).
0 = RSYNC is an output (depends on RCR.6)
1 = RSYNC is an input (only valid if elastic store enabled)
4
Receive Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
3
Unused.
Should Be set = 0 for proper operation
2
Frame Resync Criteria.
0 = resync if FAS received in error 3 consecutive times
1 = resync if FAS or bit 2 of non–FAS is received in error 3 consecutive
times
1
Sync Enable.
0 = auto resync enabled
1 = auto resync disabled
0
Resync.
When toggled from low to high, a resync is initiated. Must be
cleared and set again for a subsequent resync.
RSM
RSIO
RESE
-
FRC
SYNCE
RESYNC
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