參數(shù)資料
型號: DS21Q50N
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 74/99頁
文件大?。?/td> 325K
代理商: DS21Q50N
DS21Q50
Page 74 of 99
20. CMI (CODE MARK INVERSION)
The DS21Q50 provides a CMI interface for connection to optical transports. This interface is a unipolar 1T2B
coded signal. Ones are alternately encoded as a logical one or zero level for the full duration of the clock period.
Zeros are encode as a 0 to 1 transition at the middle of the clock period.
Figure 20-1
shows an example
data pattern and its CMI result. The control bit for enabling CMI is in the OUTAC register as shown below.
Register Name:
OUTAC
(Partially reproduced here for clarity)
Register Description:
OUTA CONTROL REGISTER
Register Address:
1A Hex
Bit #
7
6
5
4
SYM
TTLIE
CMII
CMIE
OA4
OA3
SYMBOL
BIT
TTLIE
7
.
CMII
6
CMI Invert.
0 = CMI input data not inverted
1 = CMI input data inverted
CMIE
5
Transmit and Receive CMI Enable.
0 = Transmit and Receive line interface operates in normal AMI/HDB3
mode
1 = Transmit and Receive line interface operate in CMI mode. TTIP is
CMI output and RTIP is CMI input. In this mode of operation TRING
and RRING are no-connects
OA4
4
OA3
3
OA2
2
OA1
1
OA0
0
3
2
1
0
OA2
OA1
OA0
NAME AND DESCRIPTION
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