- 您現(xiàn)在的位置：買賣IC網 > PDF目錄16264 > DS21Q59DK (Maxim Integrated Products)KIT DESIGN FOR DS21Q59 PDF資料下載
參數資料
| 型號： | DS21Q59DK |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 10/76頁 |
| 文件大小： | 0K |
| 描述： | KIT DESIGN FOR DS21Q59 |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 主要目的： | 電信，調幀器和線路接口裝置（LIU） |
| 已用 IC / 零件： | DS21Q59 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
DS21Q59 Quad E1 Transceiver
18 of 76
8.1 Power-Up Sequence
On power-up and after the supplies are stable, the DS21Q59 should be configured for operation by writing to all the
internal registers (this includes setting the test register to 00h) since the contents of the internal registers cannot be
predicted on power-up. The LIRST (CCR5.4) should be toggled from 0 to 1 to reset the line interface circuitry. (It
takes the device about 40ms to recover from the LIRST bit being toggled.) After the SYSCLK input is stable, the
ESR bits (CCR4.5 and CCR4.6) should be toggled from 0 to 1 (this step can be skipped if the elastic store is
disabled).
Register Name:
RCR
Register Description:
Receive Control Register
Register Address:
10 Hex
Bit #
7
6
5
4
3
2
1
0
Name
RSMF
RSM
RSIO
RESE
—
FRC
SYNCE
RESYNC
NAME
BIT
FUNCTION
RSMF
7
RSYNC Multiframe Function. Only used if the RSYNC pin is programmed in the
multiframe mode (RCR.6 = 1).
0 = RSYNC outputs CAS multiframe boundaries.
1 = RSYNC outputs CRC4 multiframe boundaries.
RSM
6
RSYNC Mode Select
0 = frame mode (see the timing diagrams in Section 24.1)
1 = multiframe mode (see the timing diagrams in Section 24.1)
RSIO
5
RSYNC I/O Select. (Note: This bit must be set to 0 when RCR .4 = 0.)
0 = RSYNC is an output (depends on RCR.6)
1 = RSYNC is an input (only valid if elastic store enabled)
RESE
4
Receive Elastic Store Enable
0 = elastic store is bypassed
1 = elastic store is enabled
—
3
Unused. Should be set = 0 for proper operation.
FRC
2
Frame Resync Criteria
0 = resync if FAS received in error three consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times
SYNCE
1
Sync Enable
0 = auto resync enabled
1 = auto resync disabled
RESYNC
0
Resync. When toggled from low to high, a resync is initiated. Must be cleared and
set again for a subsequent resync.
相關PDF資料 |
PDF描述 |
|---|---|
| RCM28DCTH | CONN EDGECARD 56POS DIP .156 SLD |
| EET-ED2D152EA | CAP ALUM 1500UF 200V 20% SNAP |
| RCM28DCTD | CONN EDGECARD 56POS DIP .156 SLD |
| PLE0G681MDO1 | CAP ALUM 680UF 4V 20% RADIAL |
| PLE0E561MCO1 | CAP ALUM 560UF 2.5V 20% RADIAL |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DS21Q59L | 功能描述:網絡控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q59L+ | 功能描述:網絡控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q59LN | 功能描述:網絡控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q59LN+ | 功能描述:網絡控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21S07A | 制造商:Maxim Integrated Products 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。