參數(shù)資料
型號: DS21Q59DK
廠商: Maxim Integrated Products
文件頁數(shù): 6/76頁
文件大小: 0K
描述: KIT DESIGN FOR DS21Q59
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,調(diào)幀器和線路接口裝置(LIU)
已用 IC / 零件: DS21Q59
DS21Q59 Quad E1 Transceiver
14 of 76
6. HOST INTERFACE PORT
The DS21Q59 is controlled through either a nonmultiplexed bus, a multiplexed bus, or serial interface bus by an
external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing
configurations. See Table 6-A for a description of the bus configurations. Motorola bus signals are listed in
parentheses (). See the timing diagrams in the AC Electrical Characteristics in Section 26 for more details.
Table 6-A. Bus Mode Select
PBTS
BTS1
BTS0
PARALLEL PORT MODE
0
Intel Multiplexed
0
1
Intel Nonmultiplexed
1
0
Motorola Multiplexed
1
0
1
Motorola Nonmultiplexed
X
1
0
Serial
X
1
TEST (Outputs High-Z)
6.1 Parallel Port Operation
When using the parallel interface on the DS21Q59 (BTS1 = 0) the user has the option for either multiplexed bus
operation (BTS1 = 0, BTS0 = 0) or nonmultiplexed bus operation (BTS1 = 0, BTS0 = 1). The DS21Q59 can operate
with either Intel or Motorola bus timing configurations. If the PBTS pin is wired low, Intel timing is selected; if wired
high, Motorola timing is selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in
Section 26 for more details.
6.2 Serial Port Operation
Setting the BTS1 pin = 1 and BTS0 pin = 0 enables the serial bus interface on the DS21Q59. Port read/write timing
is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See
Section 26 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 6-1, Figure 6-2,
Figure 6-3, and Figure 6-4 for more details.
Reading or writing to the internal registers requires writing one address/command byte prior to transferring register
data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1) or a write
(0). The next five bits identify the register address. The next bit is reserved and must be set to 0 for proper
operation. The last bit (MSB) of the address/command byte enables the burst mode when set to 1. The burst mode
causes all registers to be consecutively written or read.
All data transfers are initiated by driving the
CS input low. When input-clock edge select (ICES) is low, input data is
latched on the rising edge of SCLK; when ICES is high, input data is latched on the falling edge of SCLK. When
output-clock edge select (OCES) is low, data is output on the falling edge of SCLK; when OCES is high, data is
output on the rising edge of SCLK. Data is held until the next falling or rising edge. All data transfers are terminated
if the
CS input transitions high. Port control logic is disabled and SDO is tri-stated when CS is high.
Figure 6-1. Serial Port Operation Mode 1
ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK)
OCES = 1 (UPDATE SDO ON THE RISING EDGE OF SCLK)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/
W
A0
A1
A2
A3
A4
A5
B
D1
D2
D3
D4
D5
D6
SCLK
SDI
SDO
CS
LSB
MSB
D0
LSB
D7
MSB
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