參數(shù)資料
型號(hào): DS21Q59DK
廠商: Maxim Integrated Products
文件頁數(shù): 28/76頁
文件大小: 0K
描述: KIT DESIGN FOR DS21Q59
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,調(diào)幀器和線路接口裝置(LIU)
已用 IC / 零件: DS21Q59
DS21Q59 Quad E1 Transceiver
34 of 76
10.
ERROR COUNT REGISTERS
Each DS21Q59 transceiver contains a set of four counters that record bipolar (BPVs) or code violations (CVs),
errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. The E-bit
counter is reconfigured for counting errors in the PRBS pattern if receive PRBS is enabled. Each of these four
counters is automatically updated on either one-second boundaries (CCR2.70 = 0) or every 62.5ms (CCR2.7 = 1)
as determined by the timer in status register 2 (SR2.4). Hence, these registers contain performance data from
either the previous second or the previous 62.5ms. The user can use the interrupt from the one-second timer to
determine when to read these registers. The user has a full second (or 62.5ms) to read the counters before the
data is lost. The counters saturate at their respective maximum counts and do not roll over.
10.1 BPV or CV Counter
Violation count register 1 (VCR1) is the most significant word and VCR2 is the least significant word of a 16-bit
counter that records either BPVs or CVs. If CCR2.6 = 0, the VCR counts BPVs. BPVs are defined as consecutive
marks of the same polarity. In this mode, if the HDB3 mode is set for the receiver through CCR1.2, then HDB3
codewords are not counted as BPVs. If CCR2.6 = 1, the VCR counts CVs as defined in ITU O.161. CVs are
defined as consecutive BPVs of the same polarity. In most applications, the framer should be programmed to count
BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times
and is not disabled by loss-of-sync conditions. The counter saturates at 65,535 and does not roll over. The bit-error
rate on an E1 line would have to be greater than 10
-2 before the VCR would saturate.
Register Name:
VCR1, VCR2
Register Description:
Bipolar Violation Count Registers
Register Address:
00 Hex, 01 Hex
Bit #
7
6
5
4
3
2
1
0
V15
V14
V13
V12
V11
V10
V9
V8
Name
V7
V6
V5
V4
V3
V2
V1
V0
NAME
BIT
FUNCTION
V15
VCR1.7
MSB of the 16-bit code violation count.
V0
VCR2.0
LSB of the 16-bit code violation count.
10.2 CRC4 Error Counter
CRC4 count register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 16-bit
counter that records word errors in the cyclic redundancy check 4 (CRC4). Since the maximum CRC4 count in a
one-second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the
FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the CAS level. CRCCR1 and
CRCCR2 have an alternate function.
Register Name:
CRCCR1, CRCCR2
Register Description:
CRC4 Count Registers
Register Address:
02 Hex, 03 Hex
Bit #
7
6
5
4
3
2
1
0
CRC15
CRC14
CRC13
CRC12
CRC11
CRC10
CRC9
CRC8
Name
CRC7
CRC6
CRC5
CRC4
CRC/3
CRC2
CRC1
CRC0
NAME
BIT
FUNCTION
CRC15
CRCCR1.7
MSB of the 16-bit CRC4 error count.
CRC0
CRCCR2.0
LSB of the 16-bit CRC4 error count.
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