參數(shù)資料
型號: DS21Q59DK
廠商: Maxim Integrated Products
文件頁數(shù): 43/76頁
文件大?。?/td> 0K
描述: KIT DESIGN FOR DS21Q59
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,調(diào)幀器和線路接口裝置(LIU)
已用 IC / 零件: DS21Q59
DS21Q59 Quad E1 Transceiver
48 of 76
21.2 Transmit Waveshaping and Line Driving
The DS21Q59 uses a set of laser-trimmed delay lines and a precision digital-to-analog converter (DAC) to create
the waveforms that are transmitted onto the E1 line. The waveforms meet the ITU G.703 specifications
(Figure 21-3). The user selects which waveform is to be generated by properly programming the L2/L1/L0 bits in
the line interface control register (LICR). The DS21Q59 can be set up in a number of various configurations
depending on the application (Table 21-A).
Table 21-A. Line Build-Out Select in LICR
L2
L1
L0
APPLICATION
TRANSFORMER
RETURN LOSS
*
Rt (
W)
**
0
75
W normal
1:2 step-up
N.M.
0
1
120
W normal
1:2 step-up
N.M.
0
1
0
75
W with protection resistors
1:2 step-up
N.M.
2.5
0
1
120
W with protection resistors
1:2 step-up
N.M.
2.5
1
0
75
W with high return loss
1:2 step-up
21dB
6.2
1
0
1
120
W with high return loss
1:2 step-up
21dB
11.6
*N.M. = Not meaningful (return loss value too low for significance)
**See Application Note 336: Transparent Operation on T1, E1 Framers and Transceivers for details on E1 line interface design.
Because of the nature of the transmitter’s design, very little jitter (less than 0.005UIP-P broadband from 10Hz to
100kHz) is added to the jitter present on TCLK (or source used for transmit clock). Also, the waveform created is
independent of the duty cycle of TCLK. The transmitter in the device couples to the E1 transmit-shielded twisted
pair or coax through a 1:2 step-up transformer, as shown in Figure 21-1. For the devices to create the proper
waveforms, the transformer used must meet the specifications listed in Table 21-B. The line driver in the device
contains a current limiter that prevents more than 50mA (RMS) from being sourced in a 1
W load.
Table 21-B. Transformer Specifications
SPECIFICATION
RECOMMENDED VALUE
Turns Ratio
1:1 (receive) and 1:2 (transmit) ±3%
Primary Inductance
600
mH minimum
Leakage Inductance
1.0
mH maximum
Intertwining Capacitance
40pF maximum
DC Resistance
1.2
W maximum
Figure 21-1. External Analog Connections (Basic Configuration)
RTIP
RRING
TTIP
TRING
E1 TRANSMIT
LINE
DS21Q59
0.47
mF
(NONPOLARIZED)
DVDD
DVSS
0.1
mF
RVDD
RVSS
0.1
mF
TVDD
TVSS
0.1
mF
+3.3V
Rr
0.1
mF
0.01
mF
2.048MHz
MCLK
1 : 1
2 : 1
Rr
1/4
E1 RECEIVE
LINE
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