__________________________________________________________________________________________DS26900
23
4.2
Master Arbitration
The DS26900 can have one of three possible master ports: External Test Master (ETM), Test Master 1 (TM1), or
Test Master 2 (TM2). The TM1 and TM2 ports can be bidirectional based on the state of the configuration bit
TM_SLAVE. An application, which has less than three masters, can use any combination of master ports.
Table 4-2 lists the possible signal configurations and arbitrations for master. In the table, BLOCKED indicates that
the JTAG signals are ignored both to and from this port, SLAVE indicates that this port is a target for the JTAG
master, MASTER indicates the JTAG signal source port, CONFIG indicates the configuration mode for the
DS26900, and NORMAL indicates normal JTAG signal operation from master to slave.
Table 4-2. Master Arbitration
EREQ ECFG TMREQ1 TRST1 TMREQ2 TRST2
ACTIVE
MASTER
MODE
TM1
INTERFACE
MODE
TM2
INTERFACE
MODE
L
X
L
X
ETM
CONFIG
BLOCKED
L
H
L
X
L
X
ETM
NORMAL
BLOCKED
L
H
L
X
H
X
ETM
NORMAL
BLOCKED
SLAVE
L
H
X
L
X
ETM
NORMAL
SLAVE
BLOCKED
L
H
X
H
X
ETM
NORMAL
SLAVE
H
X
L
X
TM1
CONFIG
MASTER
BLOCKED
H
X
L
H
L
X
TM1
NORMAL
MASTER
BLOCKED
H
X
H
X
L
TM2
CONFIG
SLAVE
MASTER
H
X
H
X
L
H
TM2
NORMAL
SLAVE
MASTER
H
X
H
X
H
X
NONE
INACTIVE
SLAVE
Note: Slave mode of TM1 and TM2 is affected by the state of the configuration bit TM_SLAVE.
L = Connect = VSS; H = Connect = VDD; X = Don’t care
Only one master is allowed at any time. A test master that is in slave mode has the sense of all the JTAG signals
reversed (outputs become inputs, inputs become outputs, and only
TMREQ does not change), and it functions
identically to a secondary port. A test master that is blocked has its control signals ignored (the JTAG outputs are
blocked, JTAG inputs are set to a constant logic level,
TMREQ is unaffected). Since the TM ports lack a separate
configuration signal,
TRST functions as the configuration signal. To avoid glitches on the output secondary ports, all
the master signals (TMS, TDI, TDO, and CLK) should be set to logic 0 while switching the master to/from Test
Master 1 or Test Master 2. The TM1/TM2 slave interface mode will additionally be affected by the state of the
configuration bit TM_SLAVE.
If an active master is not present (
EREQ, TMREQ1, and TMREQ2 are all logic 1), the Switch TAP Controller goes
into Test-Logic-Reset and the content of the instruction register is cleared. All other registers retain their values.
The MSB of the last instruction, before clearing, is always retained in a separate register unless global reset is
asserted. The port whose address is in the Secondary Port Selection Register
(SPSR) is technically still selected,
and that port will not be affected by the state of the DPDV bit in the Device Configuration Register
(DCR). If a
different master becomes the active master, communications can resume with the port whose address is in the
Secondary Port Selection Register and whose instruction register MSB is of the proper value. The Secondary Port
Selection Register should be written with all zeros once communications with secondary ports is completed.
A DS26900 in Deselect Mode disables detection of
EREQ, TMREQ1, and TMREQ2, and the device therefore acts
as if an active master is not present. Deselect Mode is selected when the mode pins (M[1:0]) are both asserted
high.