__________________________________________________________________________________________DS26900
15
NAME
PIN
TYPE
FUNCTION
TDO2
29
I/O
Test Master 2 Test Port Serial Data Out
Master Mode = Output
Slave Mode = Input
When PREN = VDD, an internal 10k pullup resistor is connected to this pin.
TCK2
30
Ipd/O
Test Master 2 Test Port Clock
Master Mode = Input
Slave Mode = Output
When PREN = VDD, an internal 20k pulldown resistor is connected to this pin.
TRST2
31
Ipu/O
Test Master 2 Test Port Test Reset (Active Low). Asserting this pin low (when
master) puts the DS26900 into configuration mode, allowing access to the Switch
TAP Controller. Toggling
TRST2 when not the arbitrated master has no effect. This
pin does not directly affect secondary port resets.
Master Mode =
TRST2 Input
Slave Mode =
TRST2 Output
When PREN = VDD, an internal 10k pullup resistor is connected to this pin.
TMS2
32
Ipd/O
Test Master 2 Test Port Test Mode Select
Master Mode = Input
Slave Mode = Output
When PREN = VDD, an internal 20k pulldown resistor is connected to this pin.
RST
33
Ipu
Global Reset (Active Low). (Internal 10k
Pullup) A low state on this pin provides
an asynchronous reset for global registers and logic.
RST should be tied high for
normal operation.
MCI
34
O
Master Conflict Indicator (Active Low). Indicates that more than one device is
requesting to be master.
Asserted low when more than one of the
EREQ, TMREQ1, or TMREQ2 signals is
asserted low.
PTMS
35
Ipu
Periphery JTAG Chain Test Mode Select. This input must be driven to a logic level
during normal operation.
PTRST
37
I
Periphery JTAG Chain Test Reset (Active Low). During normal operation, this
signal is asserted low.
PTDO
38
O
Periphery JTAG Chain Serial Data Out
PTDI
39
I
Periphery JTAG Chain Serial Data Input. This input must be driven to a logic level
during normal operation.
PTCK
40
I
Periphery JTAG Chain Test Clock. This input must be driven to a logic level during
normal operation.
STMS10
41
O
Secondary Port 10 Test Mode Select (Internal 20k
Pulldown)
STRST10
42
O
Secondary Port 10 Test Reset (Active Low)
STCK10
43
O
Secondary Port 10 Test Clock
STDI10
44
O
Secondary Port 10 Serial Data Input
STDO10
45
Ipu
Secondary Port 10 Serial Data Out (Internal 10k
Pullup)
STMS9
46
O
Secondary Port 9 Test Mode Select (Internal 20k
Pulldown)
STRST9
47
O
Secondary Port 9 Test Reset (Active Low)
STCK9
49
O
Secondary Port 9 Test Clock
STDI9
50
O
Secondary Port 9 Serial Data Input
STDO9
51
Ipu
Secondary Port 9 Serial Data Out (Internal 10k
Pullup)
STMS8
52
O
Secondary Port 8 Test Mode Select (Internal 20k
Pulldown)
STRST8
53
O
Secondary Port 8 Test Reset (Active Low)