參數(shù)資料
型號(hào)： DS26900LN+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 47/49頁(yè)
文件大小： 0K
描述： IC JTAG MUX/SWITCH 144-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： *
功能： *
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3.14 V ~ 3.47 V
電流 - 電源： *
工作溫度： *
安裝類(lèi)型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤(pán)
__________________________________________________________________________________________DS26900
7
2. Pin Descriptions
Table 2-1. Pin Descriptions (Sorted by Function)
NAME
PIN
TYPE
FUNCTION
ETCK
4
Ipd
External Test Master Clock. In configuration mode, a falling edge on this pin clocks
data in on the ETDI pin. A falling edge on this pin clocks data out on the ETDO pin.
When PREN = VDD, a 20k pulldown resistor is connected to this pin.
ETDI
2
Ipd
External Test Master Serial Data Input. In configuration mode, data is clocked in on
this pin on the falling edge of ETCK.
When PREN = VDD, a 20k pulldown resistor is connected to this pin.
ETDO
3
O/
High
Impedance
External Test Master Serial Data Out. (High Impedance) Data is clocked out on this
pin on the falling edge of ETCK.
When PREN = VDD, a 10k pullup resistor is connected to this pin.
ECFG
5
Ipu
External Test Master Configuration (Active Low). Asserting this pin low along with
EREQ asserted low allows the External Test Master to configure the DS26900,
allowing access to the Switch TAP Controller. Toggling
ECFG when EREQ is high has
no effect.
When PREN = VDD, a 10k pullup resistor is connected to this pin.
ETMS
6
Ipu
External Test Master Test Mode Select. This pin is sampled on the rising edge of
ETCK and is used to place the port into the various defined IEEE 1149.1 states.
When PREN = VDD, a 10k pullup resistor is connected to this pin.
EREQ
1
Ipu
External Test Master Request (Active Low). (Internal 10k
Pullup) When active,
this pin selects the external test port as the master. When switching
EREQ, none of
the master clocks should be toggling.
MGNT0
144
O
Master Grant 0 (Active Low). Asserted low when the external test master is the
arbitrated master.
TCK1
22
Ipd/O
Test Master 1 Test Port Clock
Master Mode = Input
Slave Mode = Output
When PREN = VDD, an internal 20k pulldown resistor is connected to this pin.
TDI1
20
Ipu/O
Test Master 1 Test Port Serial Data Input
Master Mode = Input
Slave Mode = Output
When PREN = VDD, an internal 10k pullup resistor is connected to this pin.
TDO1
21
I/O
Test Master 1 Test Port Serial Data Out
Master Mode = Output
Slave Mode = Input
When PREN = VDD, an internal 10k pullup resistor is connected to this pin.
TRST1
23
Ipu/O
Test Master 1 Test Port Test Reset (Active Low). Asserting this pin low (when
master) puts the DS26900 into configuration mode, allowing access to the Switch
TAP Controller. Toggling
TRST1 when not the arbitrated master has no effect. This
pin does not directly affect secondary port resets.
Master Mode =
TRST1 Input
Slave Mode =
TRST1 Output
When PREN = VDD, an internal 10k pullup resistor is connected to this pin.
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參數(shù)描述
DS26900LN+ 功能描述:多路器開(kāi)關(guān) IC JTAG MUX RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開(kāi)關(guān)數(shù)量:4 開(kāi)啟電阻（最大值）:7 Ohms 開(kāi)啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 傳播延遲時(shí)間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UQFN-16
DS26900N+ 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:JTAG Multiplexer/Switch
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DS26C31 DIE 制造商:Texas Instruments 功能描述:
DS26C31_BBA3026X WAF 制造商:Texas Instruments 功能描述:
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