
__________________________________________________________________________________________DS26900
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6. Configuration Mode
Configuration mode is used by a master to program the options in the DS26900 switch and to configure the
address of the secondary port. Configuration mode for the ETM is accomplished when
EREQ and ECFG are both
asserted low. While
EREQ and ECFG are asserted low, the secondary slave ports JTAG signals are not allowed to
toggle (
STRSTn can only be asserted low by the Switch TAP Controller port reset instructions). In configuration
mode, the master has access to the configuration TAP controller in the DS26900. When
EREQ is asserted low and
ECFG is asserted high, the JTAG signal group toggles normally and the ETM acts as the master.
Configuration mode for the Test Master 1 and Test Master 2 is accomplished when
TREQn and TRSTn are both
asserted low. While
TMREQ and TRSTn are both asserted low, the JTAG signal group remains static. In
configuration mode, the master has access to the configuration TAP controller in the DS26900. To set the target
(slave) port, the port address must be written to the Secondary Port Selection Register
(SPSR).
There is only one configuration mode for the DS26900. As a result, the master can set a configuration that remains
valid for any master secondary port until reconfigured or
RST is asserted low.
6.1
Switch TAP Controller
The Switch TAP Controller is implemented as standard IEEE 1149.1 TAP controller. See Section
9.2 and
6.1.1 Switch Instructions
Table 6-1. Switch TAP Instruction Codes
INSTRUCTIONS
SELECTED REGISTER
SINGLE-PACKAGE AND
CASCADE MASTER
INSTRUCTION CODES
CASCADE EXTENSION
INSTRUCTION CODES
IDCODE
00000
10000
PORT_DET
Port Detection Register
(PDR)00001
10001
PORT_SEL
Secondary Port Selection
00010
10010
GPIO_CFG
GPIO Configuration and Write
00011
10011
GPIO_READ
00100
10100
CONFIG
Device Configuration Register
00101
10101
SCRATCH_1
00110
10110
SCRATCH_2
00111
10111
PORT_RST
Port Reset for a Selected Port
01000
11000
NOP
No Operation
01001–01110
11001–11110
ALL_PORTS_RST
Global Port Test Reset
01111
11111
When performing a register write, the current value of a register is shifted out while the new register value is being
shifted in. For read-only registers, some bit value must be shifted in (which is ignored) to shift out the current
register value.