參數(shù)資料
型號： DS26900LN+
廠商： Maxim Integrated Products
文件頁數(shù)： 35/49頁
文件大?。?/td> 0K
描述： IC JTAG MUX/SWITCH 144-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： *
功能： *
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3.14 V ~ 3.47 V
電流 - 電源： *
工作溫度： *
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
__________________________________________________________________________________________DS26900
40
remains at its current value. On the rising edge of PTCLK, the controller goes to the Shift-DR state if PTMS is low
or it to the Exit1-DR state if PTMS is high.
Shift-DR. The test data register selected by the current instruction is connected between PTDI and PTDO and
shifts data one stage towards its serial output on each rising edge of PTCLK. If a test register selected by the
current instruction is not placed in the serial path, it maintains its previous state.
Exit1-DR. While in this state, a rising edge on PTCLK with PTMS high puts the controller in the Update-DR state,
which terminates the scanning process. A rising edge on PTCLK with PTMS low puts the controller in the Pause-
DR state.
Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction retain their previous state. The controller remains in this state while PTMS is low. A rising edge on
PTCLK with PTMS high puts the controller in the Exit2-DR state.
Exit2-DR. While in this state, a rising edge on PTCLK with PTMS high puts the controller in the Update-DR state
and terminates the scanning process. A rising edge on PTCLK with PTMS low puts the controller in the Shift-DR
state.
Update-DR. A falling edge on PTCLK while in the Update-DR state latches the data from the shift register path of
the Test registers into the data output latches. This prevents changes at the parallel output due to changes in the
shift register. A rising edge on PTCLK with PTMS low puts the controller in the Run-Test-Idle state. With PTMS
high, the controller enters the Select-DR-Scan state.
Select-IR-Scan. All test registers retain their previous state. The instruction register remains unchanged during this
state. With PTMS low, a rising edge on PTCLK moves the controller into the Capture-IR state and initiates a scan
sequence for the Instruction register. PTMS high during a rising edge on PTCLK puts the controller back into the
Test-Logic-Reset state.
Capture-IR. The Capture-IR state is used to load the shift register in the Instruction register with a fixed value. This
value is loaded on the rising edge of PTCLK. If PTMS is high on the rising edge of PTCLK, the controller enters the
Exit1-IR state. If PTMS is low on the rising edge of PTCLK, the controller enters the Shift-IR state.
Shift-IR. In this state, the shift register in the instruction register is connected between PTDI and PTDO and shifts
data one stage for every rising edge of PTCLK towards the serial output. The parallel register, as well as all test
registers, remains at its previous states. A rising edge on PTCLK with PTMS high moves the controller to the Exit1-
IR state. A rising edge on PTCLK with PTMS low keeps the controller in the Shift-IR state while moving data one
stage through the Instruction shift register.
Exit1-IR. A rising edge on PTCLK with PTMS low puts the controller in the Pause-IR state. If PTMS is high on the
rising edge of PTCLK, the controller enters the Update-IR state and terminates the scanning process.
Pause-IR. Shifting of the Instruction register is halted temporarily. With PTMS high, a rising edge on PTCLK puts
the controller in the Exit2-IR state. The controller remains in the Pause-IR state if PTMS is low during a rising edge
on PTCLK.
Exit2-IR. A rising edge on PTCLK with PTMS high put the controller in the Update-IR state. The controller loops
back to the Shift-IR state if PTMS is low during a rising edge of PTCLK in this state.
Update-IR. The instruction shifted into the instruction shift register is latched into the parallel output on the falling
edge of PTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A
rising edge on PTCLK with PTMS low, puts the controller in the Run-Test-Idle state. With PTMS high, the controller
enters the Select-DR-Scan state.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS26900LN+ 功能描述:多路器開關(guān) IC JTAG MUX RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關(guān)數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 傳播延遲時(shí)間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UQFN-16
DS26900N+ 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:JTAG Multiplexer/Switch
DS26C31 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CMOS QUAD TRI-STATE DIFFERENTIAL LINE DRIVER
DS26C31 DIE 制造商:Texas Instruments 功能描述:
DS26C31_BBA3026X WAF 制造商:Texas Instruments 功能描述:
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