__________________________________________________________________________________________DS26900
24
The master grant signals,
MGNT0, MGNT1, and MGNT2, are generated by the master arbitrator. These signals are
available to the appropriate master to indicate that it has control. The
MCI output is asserted low to indicate this
possible conflict should more than one of the REQ signals be asserted low.
An active signal indicates the active (selected) device by asserting
ACT low. The ACT pin is asserted low under the
Table 4-3.
ACT Output States
M1 PIN
M0 PIN
INSTRUCTION REGISTER
VALUE
IS THERE AN
ACTIVE MASTER?
ACT
OUTPUT
0
0XXXX
Yes
0
1XXXX
Yes
1
0
1
0XXXX
Yes
0
1
1XXXX
Yes
1
0
0XXXX
Yes
1
0
1XXXX
Yes
0
1
XXXXX
X
1
X
XXXXX
No
1
X = Don’t care
4.2.1 Missing Test Master or Unused Test Master Port
An unused or missing test master has its
TMREQ signal tied high by the user (DS26900 has a pullup on that input
pin so the user can leave this pin unconnected), which puts that port into slave mode.
4.2.2 Detection of the Presence of Secondary Ports
The presence of secondary ports is detected by sensing the logic level present on the STMSn signal (the STMSn
signal on a port should have a pullup) on each secondary port and test master port. Logic 1 is latched into the
20-bit Port Detection Register
(PDR) for each pullup that is sensed. The STMSn and TMSn signals are sensed and
the Port Detection Register
(PDR) is updated each time the Switch TAP Controller passes out of the reset state.
(TMSn signals can only be sensed on TM1/TM2 slave-mode ports.)
4.2.3 Selection of the Secondary Port
Selection of the secondary port (“slave”) is accomplished by writing a 5-bit address into the Secondary Port
Selection Register
(SPSR). Due to the star configuration, only one port can be selected at a time. Ports that are not
detected as being present by sensing the pullup on the secondary port’s TMS pin can still be selected, and the
signals will be sent to that port.
This 5-bit secondary port selection address is complemented and used to generate the selected slave port indicator
bits (
SSPI[4:0]). These bits can be used as a visual indicator as to which slave port has been selected.
Once communications with a secondary port has been completed, the Secondary Port Selection Register
(SPSR)should be set to all zeros. If not, the selected port address will not respond to the DPDV bit of the Device
Configuration Register
(DCR). This is true if an active master is present or not.
4.2.4 Master Port/Secondary Port Path Timing Description
Each of the arbitrated masters passes into a 3 x 1 multiplexer and then a 1 x 20 multiplexer, such that any of the
three possible masters can connect to any of the 20 possible secondary ports (18 secondary ports plus the test
master ports when available). The test clock (TCK), test mode select (TMS), test data in (TDI), and test data out