參數(shù)資料
型號(hào)： DS26900LN+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 39/49頁(yè)
文件大?。?/td> 0K
描述： IC JTAG MUX/SWITCH 144-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： *
功能： *
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3.14 V ~ 3.47 V
電流 - 電源： *
工作溫度： *
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
__________________________________________________________________________________________DS26900
44
11. AC Timing
Unless otherwise noted, all timing numbers assume 20pF test load on output signals, 40pF test load on bus
signals.
11.1 Switch TAP Controller Interface Timing
Table 11-1. Switch TAP Controller Interface Timing
(VDD = 3.3V ±5%, TA = -40°C to +85°C.) (See Figure 11-1.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
ETCK, TCK1, TCK2 Clock Period
t1
25
ns
30% DC
ETCK, TCK1, TCK2 Clock Low Time
t2
17.5
ns
ETCK, TCK1, TCK2 Clock High Time
t3
7.5
ns
ETCK to ETDI, ETMS Setup Time
TCK1 to TDI1, TMS1 Setup Time
TCK2 to TDI2, TMS2 Setup Time
t4
3
ns
ETCK to ETDI, ETMS Hold Time
TCK1 to TDI1, TMS1 Hold Time
TCK2 to TDI2, TMS2 Hold Time
t5
3
ns
ETCK to ETDO Delay
TCK1 to TDO1 Delay
TCK2 to TDO2 Delay
t6
15
ns
ETCK to ETDO High-Impedance Delay
TCK1 to TDO1 High-Impedance Delay
TCK2 to TDO2 High-Impedance Delay
t7
17.5
ns
Note 1:
TCK should be stopped low.
Note 2:
Interface timing in Table 11-1 is to/from the arbitrated master.
Note 3:
TCK corresponds to each master port clock when being used to configure the core JTAG controller, e.g., ETCK or TCK1 or TCK2.
Note 4:
TDI, TMS correspond to the master port TDI, TMS when being used to configure the core JTAG controller, e.g., ETDI, ETMS or
TDI1, TMS1 or TDI2, TMS2.
Note 5:
TDO corresponds to the master port TDO when being used to configure the core JTAG controller, e.g., ETDO or TDO1 or TDO2.
Note 6:
The configuration signals (
TRST1, TRST2, ECFG) and the master request signals (TMREQ1, TMREQ2, EREQ) are asynchronous.
TCK, TDI, TMS should be low when switching masters to avoid the possibility of glitching the secondary port whose address is in
the Secondary Port Selection Register (SPSR). Another method to avoid glitching the secondary port is to set the Secondary Port
Selection Register (SPSR) to 00000 when changing the arbitrated master.
Figure 11-1. Switch TAP Controller Interface Timing Diagram
ETCK
TCK1
TCK2
ETDO
TDO1
TDO2
T2
T3
T1
T4
ETDI, ETMS
TDI1, TMS1
TDI2, TMS2
T5
T6
T7
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DS26900LN+ 功能描述:多路器開關(guān) IC JTAG MUX RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關(guān)數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 傳播延遲時(shí)間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UQFN-16
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