__________________________________________________________________________________________DS26900
11
NAME
PIN
TYPE
FUNCTION
SSPI4
8
O
Selected Secondary Port Indicator Bit 4 (Active Low). Along with pins
SSPI3,
SSPI2, SSPI1, and SSPI0, this pin provides a hardware indication of the selected
secondary port. See
Table 7-2 for more information.
SSPI3
9
O
Selected Secondary Port Indicator Bit 3 (Active Low). Along with pins
SSPI4,
SSPI2, SSPI1, and SSPI0, this pin provides a hardware indication of the selected
secondary port. See
Table 7-2 for more information.
SSPI2
10
O
Selected Secondary Port Indicator Bit 2 (Active Low). Along with pins
SSPI4,
SSPI3, SSPI1, and SSPI0, this provides a hardware indication of the selected
secondary port. See
Table 7-2 for more information.
SSPI1
11
O
Selected Secondary Port Indicator Bit 1 (Active Low). Along with pins
SSPI4,
SSPI3, SSPI2, and SSPI0, this pin provides a hardware indication of the selected
secondary port. See
Table 7-2 for more information.
SSPI0
12
O
Selected Secondary Port Indicator Bit 0 (Active Low). Along with pins
SSPI4,
SSPI3, SSPI2, and SSPI1, this pin provides a hardware indication of the selected
secondary port. See
Table 7-2 for more information.
GPIO[3]
14
Ipd/O
General-Purpose Input/Output Bit 3. (Internal 20k
Pulldown) This pin is a general-
purpose input/output, which can be read or driven via a register bit. This pin is in input
mode after a global reset.
GPIO[2]
15
Ipd/O
General-Purpose Input/Output Bit 2. (Internal 20k
Pulldown) This pin is a general-
purpose input/output, which can be read or driven via a register bit. This pin is in input
mode after a global reset.
GPIO[1]
16
Ipd/O
General-Purpose Input/Output Bit 1. (Internal 20k
Pulldown) This pin is a general-
purpose input/output, which can be read or driven via a register bit. This pin is in input
mode after a global reset.
GPIO[0]
17
Ipd/O
General-Purpose Input/Output Bit 0. (Internal 20k
Pulldown) This pin is a general-
purpose input/output, which can be read or driven via a register bit. This pin is in input
mode after a global reset.
RST
33
Ipu
Global Reset (Active Low). (Internal 10k
Pullup) A low state on this pin provides
an asynchronous reset for global registers and logic.
RST should be tied high for
normal operation.
TEST
62
Ipu
Test Enable (Active Low). (Internal 10k
Pullup) Factory test input. TEST must be
tied high or unconnected for normal operation.
HIZ
143
I
Output High-Impedance Enable (Active Low). When this pin is asserted low,
internal pullup and pulldown resistors are disabled, all outputs are put into high-
impedance mode, and master request inputs (
EREQ, TMREQ1, TMREQ2) are
disabled.
PTRST must also be asserted logic 0.
M[1]
141
Ipd
Mode Select Bit 1. (Internal 20k
Pulldown) Selects mode of operation of the device
(Single-Package, Cascade-Master, Cascade-Extension, or Deselect.
M[0]
142
Ipd
Mode Select Bit 0. (Internal 20k
Pulldown) Selects mode of operation of the device
(Single-Package, Cascade-Master, Cascade-Extension, or Deselect).
MCI
34
O
Master Conflict Indicator (Active Low). Indicates that more than one device is
requesting to be master.
Asserted low when more than one of the
EREQ, TMREQ1, or TMREQ2 signals is
asserted low.
DPDV
96
O
Deselected Port Data Value. This pin directly indicates the state of the DPDV bit in
the Device Configuration Register
(DCR).PTCK
40
I
Periphery JTAG Chain Test Clock. This input must be driven to a logic level during
normal operation.
PTDI
39
I
Periphery JTAG Chain Serial Data Input. This input must be driven to a logic level
during normal operation.
PTDO
38
O
Periphery JTAG Chain Serial Data Out