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| 型號： | DSP56303VL100B1 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 32/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 100MHZ 196-BGA |
| 標準包裝： | 630 |
| 系列： | DSP563xx |
| 類型： | 定點 |
| 接口： | 主機接口，SSI，SCI |
| 時鐘速率： | 100MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 24kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應商設備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
iii
Features
Table 1 lists the features of the DSP56303 device.
Table 1. DSP56303 Features
Feature
Description
High-Performance
DSP56300 Core
100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal
Object code compatible with the DSP56000 core with highly parallel instruction set
Data arithmetic logic unit (Data ALU) with fully pipelined 24
× 24-bit parallel multiplier-accumulator (MAC),
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG)
test access port (TAP)
Internal Peripherals
Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
Serial communications interface (SCI) with baud rate generator
Triple timer module
Up to thirty-four programmable general-purpose input/output (GPIO) pins, depending on which peripherals
are enabled
Internal Memories
192
× 24-bit bootstrap ROM
8 K
× 24-bit RAM total
Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
External Memory
Expansion
Data memory expansion to two 256 K
× 24-bit word memory spaces using the standard external address
lines
Program memory expansion to one 256 K
× 24-bit words memory space using the standard external
address lines
External memory expansion port
Chip select logic for glueless interface to static random access memory (SRAMs)
Internal DRAM Controller for glueless interface to dynamic random access memory (DRAMs)
Power Dissipation
Very low-power CMOS design
Wait and Stop low-power standby modes
Fully static design specified to operate down to 0 Hz (dc)
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-
dependent)
Packaging
144-pin TQFP package in lead-free or lead-bearing versions
196-pin molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions
Program RAM
Size
Instruction
Cache Size
X Data RAM
Size
Y Data RAM
Size
Instruction
Cache
Switch Mode
4096
× 24-bit
0
2048
× 24-bit
2048
× 24-bit
disabled
3072
× 24-bit
1024
× 24-bit
2048
× 24-bit
2048
× 24-bit
enabled
disabled
2048
× 24-bit
0
3072
× 24-bit
3072
× 24-bit
disabled
enabled
1024
× 24-bit
1024
× 24-bit
3072
× 24-bit
3072
× 24-bit
enabled
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