- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1917 > DSP56303VL100B1 (Freescale Semiconductor)IC DSP 24BIT 100MHZ 196-BGA PDF資料下載
參數(shù)資料
| 型號： | DSP56303VL100B1 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 98/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 100MHZ 196-BGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 系列： | DSP563xx |
| 類型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，SSI，SCI |
| 時鐘速率： | 100MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 24kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁當(dāng)前第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁
External Memory Expansion Port (Port A)
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
1-5
1.5.2
External Data Bus
1.5.3
External Bus Control
Table 1-7.
External Data Bus Signals
Signal
Name
Type
State
During
Reset
State
During Stop
or Wait
Signal Description
D[0–23]
Input/ Output
Ignored Input
Last state:
Input: Ignored
Output:
Tri-stated
Data Bus—When the DSP is the bus master, D[0–23] are active-high,
bidirectional input/outputs that provide the bidirectional data bus for external
program and data memory accesses. Otherwise, D[0–23] are tri-stated.
Table 1-8.
External Bus Control Signals
Signal
Name
Type
State During Reset,
Stop, or Wait
Signal Description
AA[0–3]
RAS[0–3]
Output
Tri-stated
Address Attribute—When defined as AA, these signals can be used as chip selects or
additional address lines. The default use defines a priority scheme under which only
one AA signal can be asserted at a time. Setting the AA priority disable (APD) bit (Bit
14) of the Operating Mode Register, the priority mechanism is disabled and the lines
can be used together as four external lines that can be decoded externally into 16 chip
select signals.
Row Address Strobe—When defined as RAS, these signals can be used as RAS for
DRAM interface. These signals are tri-statable outputs with programmable polarity.
RD
Output
Tri-stated
Read Enable—When the DSP is the bus master, RD is an active-low output that is
asserted to read external memory on the data bus (D[0–23]). Otherwise, RD is tri-
stated.
WR
Output
Tri-stated
Write Enable—When the DSP is the bus master, WR is an active-low output that is
asserted to write external memory on the data bus (D[0–23]). Otherwise, the signals
are tri-stated.
TA
Input
Ignored Input
Transfer Acknowledge—If the DSP56303 is the bus master and there is no external
bus activity, or the DSP56303 is not the bus master, the TA input is ignored. The TA
input is a data transfer acknowledge (DTACK) function that can extend an external bus
cycle indefinitely. Any number of wait states (1, 2. . .infinity) can be added to the wait
states inserted by the bus control register (BCR) by keeping TA deasserted. In typical
operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion
of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle
completes one clock period after TA is asserted synchronous to CLKOUT. The number
of wait states is determined by the TA input or by the BCR, whichever is longer. The
BCR can be used to set the minimum number of wait states in external bus cycles.
To use the TA functionality, the BCR must be programmed to at least one wait state. A
zero wait state access cannot be extended by TA deassertion; otherwise, improper
operation may result. TA can operate synchronously or asynchronously depending on
the setting of the TAS bit in the Operating Mode Register. TA functionality cannot be
used during DRAM type accesses; otherwise improper operation may result.
BR
Output
Reset: Output
(deasserted)
State during Stop/Wait
depends on BRH bit
setting:
BRH = 0: Output,
deasserted
BRH = 1: Maintains last
state (that is, if asserted,
remains asserted)
Bus Request—Asserted when the DSP requests bus mastership. BR is deasserted
when the DSP no longer needs the bus. BR may be asserted or deasserted
independently of whether the DSP56303 is a bus master or a bus slave. Bus “parking”
allows BR to be deasserted even though the DSP56303 is the bus master. (See the
description of bus “parking” in the BB signal description.) The bus request hold (BRH)
bit in the BCR allows BR to be asserted under software control even though the DSP
does not need the bus. BR is typically sent to an external bus arbitrator that controls the
priority, parking, and tenure of each master on the same external bus. BR is affected
only by DSP requests for the external bus, never for the internal bus. During hardware
reset, BR is deasserted and the arbitration is reset to the bus slave state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56311VF150B1 | IC DSP 24BIT 150MHZ 196-BGA |
| DSP56321VF200R2 | IC DSP 24BIT 200MHZ 196-BGA |
| DSP56852VFE | IC DSP 16BIT 120MHZ 81-MAPBGA |
| DSP56854FGE | IC DSP 16BIT 120MHZ 128-LQFP |
| DSP56855BUE | IC DSP 16BIT 120MHZ 100-LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56304GC66 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:24-Bit Digital Signal Processor |
| DSP56304GC80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:24-Bit Digital Signal Processor |
| DSP56304PV66 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:24-Bit Digital Signal Processor |
| DSP56304PV80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:24-Bit Digital Signal Processor |
| DSP56305DS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56305 Single Chip Channel Codec Digital Signal Processor Data Sheet |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。