參數(shù)資料
型號(hào): DSP56303VL100B1
廠商: Freescale Semiconductor
文件頁數(shù): 42/108頁
文件大小: 0K
描述: IC DSP 24BIT 100MHZ 196-BGA
標(biāo)準(zhǔn)包裝: 630
系列: DSP563xx
類型: 定點(diǎn)
接口: 主機(jī)接口,SSI,SCI
時(shí)鐘速率: 100MHz
非易失內(nèi)存: ROM(576 B)
芯片上RAM: 24kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 196-LBGA
供應(yīng)商設(shè)備封裝: 196-MAPBGA(15x15)
包裝: 托盤
AC Electrical Characteristics
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
2-19
Figure 2-17.
DRAM Out-of-Page Wait State Selection Guide
Table 2-11.
DRAM Out-of-Page and Refresh Timings, Eleven Wait States1,2
No.
Characteristics
Symbol
Expression3
100 MHz
Unit
Min
Max
157
Random read or write cycle time
tRC
12
× T
C
120.0
ns
158
RAS assertion to data valid (read)
tRAC
6.25
× TC 7.0
55.5
ns
159
CAS assertion to data valid (read)
tCAC
3.75
× TC 7.0
30.5
ns
160
Column address valid to data valid (read)
tAA
4.5
× T
C 7.0
38.0
ns
161
CAS deassertion to data not valid (read hold time)
tOFF
0.0
ns
162
RAS deassertion to RAS assertion
tRP
4.25
× TC 4.0
38.5
ns
163
RAS assertion pulse width
tRAS
7.75
× T
C 4.0
73.5
ns
164
CAS assertion to RAS deassertion
tRSH
5.25
× TC 4.0
48.5
ns
165
RAS assertion to CAS deassertion
tCSH
6.25
× TC 4.0
58.5
ns
166
CAS assertion pulse width
tCAS
3.75
× T
C 4.0
33.5
ns
167
RAS assertion to CAS assertion
tRCD
2.5
× TC ± 4.0
21.0
29.0
ns
168
RAS assertion to column address valid
tRAD
1.75
× TC ± 4.0
13.5
21.5
ns
169
CAS deassertion to RAS assertion
tCRP
5.75
× T
C 4.0
53.5
ns
170
CAS deassertion pulse width
tCP
4.25
× TC – 6.0
36.5
ns
171
Row address valid to RAS assertion
tASR
4.25
× TC 4.0
38.5
ns
Chip Frequency
(MHz)
DRAM Type
(tRAC ns)
100
80
70
50
66
80
100
4 Wait States
8 Wait States
11 Wait States
15 Wait States
Note:
This figure should be used for primary selection. For exact and
detailed timings, see the following tables.
60
40
120
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