Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 Freescale Semico" />
參數(shù)資料
型號(hào): DSPB56725CAF
廠商: Freescale Semiconductor
文件頁數(shù): 14/48頁
文件大小: 0K
描述: IC DSP 24BIT 80LQFP
標(biāo)準(zhǔn)包裝: 90
系列: DSP56K/Symphony
類型: 音頻處理器
接口: 主機(jī)接口,I²C,SAI,SPI
時(shí)鐘速率: 200MHz
非易失內(nèi)存: 外部
芯片上RAM: 112kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤
Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
Freescale Semiconductor
21
Figure 15 shows the SPI slave timing (CPHA = 1).
Figure 15. SPI Slave Timing (CPHA = 1)
1.2.2
Serial Host Interface (SHI) I2C Protocol Timing
Table 10 lists the SHI I2C protocol timing diagram.
Table 10. SHI I2C Protocol Timing
Standard I2C
No.
Characteristics1,2,3,4,5
Symbol/
Expression
Standard
Fast-Mode
Unit
Min
Max
Min
Max
XX
Tolerable Spike Width on SCL or SDA
Filters Bypassed
Very Narrow Filters enabled
Narrow Filters enabled
Wide Filters enabled.
0
10
50
100
0
10
50
100
ns
44
SCL clock frequency
FSCL
100
400
kHz
44
SCL clock cycle
TSCL
10
2.5
μs
45
Bus free time
TBUF
4.7
1.3
μs
46
Start condition set-up time
TSUSTA
4.7
0.6
μs
SS
(Input)
SCK (CPOL = 0)
(Input)
SCK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
HREQ
(Output)
23
24
25
26
25
24
31
33
29
30
37
34
32
29
28
27
33
30
36
MSB
LSB
MSB
LSB
Valid
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