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參數(shù)資料
| 型號： | DSPB56725CAF |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 16/48頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | DSP56K/Symphony |
| 類型： | 音頻處理器 |
| 接口： | 主機(jī)接口，I²C，SAI，SPI |
| 時(shí)鐘速率： | 200MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 112kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.00V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
Freescale Semiconductor
23
1.2.3
Programming the SHI I2C Serial Clock
The programmed serial clock cycle, TI2CCP, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock
control register).
The expression for T I2CCP is
T I2CCP = [TC × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
Eqn. 4
where
— HRS is the prescaler rate select bit. When HRS is cleared, the fixed
divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.
— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be
selected.
In I2C mode, the user may select a value for the programmed serial clock cycle from
6
× TC (if HDM[7:0] = $02 and HRS = 1)
Eqn. 5
to
4096
× TC (if HDM[7:0] = $FF and HRS = 0)
Eqn. 6
The programmed serial clock cycle (TI2CCP) should be chosen in order to achieve the desired SCL serial clock cycle (TSCL), as
shown in next.
TI2CCP + 3 × TC + 45ns + TR
(Nominal, SCL Serial Clock Cycle (TSCL) generated as master)
Eqn. 7
60
HREQ in assertion to first SCL edge
Filters bypassed
Very Narrow filters enabled
Narrow filters enabled
Wide filters enabled
TAS;RQI
4327
4317
4282
4227
—
927
917
877
827
—
ns
61
First SCL edge to HREQ is not asserted
(HREQ in hold time.)
tHO;RQI
0.0
—
0.0
—
ns
Note:
1. VCORE_VDD = 1.00± 0.05 V; TJ = –40° C to 100° C, CL = 50 pF
2. Pull-up resistor: R P (min) = 1.5 k
Ω
3. Capacitive load: C b (max) = 50 pF
5. All times assume noise free inputs
5. All times assume internal clock frequency of 200 MHz
6. SHI_1 specs match those of SHI
7. The numbers listed are based on the module/pad design and its characteristics during output. The module is compliant with
I2C standard, so the module should receive I2C bus compliant signal without any issue.
Table 10. SHI I2C Protocol Timing (Continued)
Standard I2C
No.
Characteristics1,2,3,4,5
Symbol/
Expression
Standard
Fast-Mode
Unit
Min
Max
Min
Max
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