Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 Freescale Semico" />
參數(shù)資料
型號(hào): DSPB56725CAF
廠(chǎng)商: Freescale Semiconductor
文件頁(yè)數(shù): 30/48頁(yè)
文件大?。?/td> 0K
描述: IC DSP 24BIT 80LQFP
標(biāo)準(zhǔn)包裝: 90
系列: DSP56K/Symphony
類(lèi)型: 音頻處理器
接口: 主機(jī)接口,I²C,SAI,SPI
時(shí)鐘速率: 200MHz
非易失內(nèi)存: 外部
芯片上RAM: 112kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.00V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤(pán)
Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
Freescale Semiconductor
36
Table 17 lists the EMC timing parameters with EMC PLL bypassed.
Table 17. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4)
Parameter
Symbol
Min
Max
Unit
LCLK cycle time
Tclk
4
× Tc
—ns
Input setup to LCLK (except LGTA/LUPWAIT)
Tin_s
8—
ns
Input hold from LCLK (except LGTA/LUPWAIT)1
Tin_h
–1
ns
LGTA valid time
Tgta
22
ns
LUPWAIT valid time
Tupwait
22
ns
LALE negedge to LAD (address phase) invalid (address latch hold
time)
Tale_h
4—
ns
LALE valid time
Tale
14
ns
Output setup from LCLK (except LAD[23:0] and LALE)
Tout_s
9—
ns
Output hold from LCLK (except LAD[23:0] and LALE)
Tout_h
8—
ns
LAD[23:0] output setup from LCLK
Tad_s
8—
ns
LAD[23:0] output hold from LCLK
Tad_h
7—
ns
LCLK to output high impedance for LAD[23:0]
Tad_z
—8.1
ns
Note: Negative hold time means the signal could be invalid before LCLK rising edge.
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