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參數(shù)資料
| 型號： | DSPB56725CAF |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 41/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | DSP56K/Symphony |
| 類型： | 音頻處理器 |
| 接口： | 主機(jī)接口，I²C，SAI，SPI |
| 時鐘速率： | 200MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 112kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.00V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
Freescale Semiconductor
46
5
Product Documentation
Table 21 lists the documents that provide a complete description of the DSP56724/DSP56725 devices and are required to design
properly with the part. Documentation is available from a local Freescale Semiconductor, Inc. (formerly Motorola) distributor,
semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source
for the latest information).
6
Revision History
Table 22 summarizes revisions to this document.
Table 21. DSP56724 / DSP56725 Documentation
Document Name
Description
Order Number
DSP56300 Family Manual
Detailed description of the 56300-family architecture and the 24-bit
core processor and instruction set
DSP56724/DSP56725 Reference Manual Detailed description of memory, peripherals, and interfaces
DSP56724RM
DSP56724 Product Brief
Brief description of the DSP56724 device
DSP56724PB
DSP56725 Product Brief
Brief description of the DSP56725 device
DSP56725PB
DSP56724/DSP56725 Data Sheet
Electrical and timing specifications; pin and package descriptions
(this document)
DSP56724
Table 22. Revision History
Revision
Date
Description
2
3/2009
In Table 9, “Serial Host Interface SPI Protocol Timing,” updated values for Nos. 24, 25,
27, 33, 34, and 39. Removed 40 and renumbered subsequent items accordingly.
In Table 11, “Enhanced Serial Audio Interface Timing,” for No. 71 changed 12.0 to 0.
1
12/2008
Modified values and removed rows in Table 4, “DC Electrical Characteristics.”
Removed “IO_VDD_25” from Figure 4, “Prevent High Current Conditions by Applying
In Table 7, “Reset, Stop, Mode Select, and Interrupt Timing,” for No. 15, changed 10 to
12, and for No. 16, changed 4 to 7.
In Table 9, “Serial Host Interface SPI Protocol Timing,” updated values.
In Table 10, “SHI I2C Protocol Timing,” added note 7 and changed Max values for No. 50
to 1000 and 300; in addition, updated the values for note 1.
In Table 11, “Enhanced Serial Audio Interface Timing,” for No. 82, changed 19 to 15; for
No. 83, changed 20 to 15; for No. 86, changed 18 to 25; for No. 87, changed 21 to 25.
Removed Section 1.2.5, “Timer Timing.”
“LSYNC_IN (except LGTA/LUPWAIT),” changed 2 to 3.
“LCLK to output high impedance for LAD [23:0],” changed 9 to 8.1.
LCLK to output high impedance for LAD [23:0],” changed 19 to 17.1
In Table 19, “Ordering Information,” added rows for DSPB56724CAG and
DSPB56725CAF, and changed “DSPA56724AG” to “DSPB56724AG.”
0
6/2008
Initial public release.
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