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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
Freescale Semiconductor
31
Figure 22 shows the text clock input timing diagram.
Figure 22. Test Clock Input Timing Diagram
Figure 23 shows the debugger port timing diagram.
Figure 23. Debugger Port Timing Diagram
TCK
(Input)
VM
VIH
VIL
109
110
111
TCK
(Input)
Data
Inputs
Data
Outputs
Data
Outputs
Data
Outputs
VIH
VIL
113
112
114
115
114
Input Data Valid
Output Data Valid
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