Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 Freescale Semico" />
參數(shù)資料
型號(hào)： DSPB56725CAF
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 3/48頁(yè)
文件大小： 0K
描述： IC DSP 24BIT 80LQFP
標(biāo)準(zhǔn)包裝： 90
系列： DSP56K/Symphony
類型： 音頻處理器
接口： 主機(jī)接口，I²C，SAI，SPI
時(shí)鐘速率： 200MHz
非易失內(nèi)存： 外部
芯片上RAM： 112kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.00V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
Freescale Semiconductor
11
Table 6 lists the clock operation.
1.1.9
Reset, Stop, Mode Select, and Interrupt Timing
Table 7 lists the reset, stop, mode select, and interrupt timing.
Table 6. Clock Operation
No.
Characteristics
Symbol
Min
Max
Units
6
EXTAL input high 1
(40% to 60% duty cycle)
Crystal oscillator
Square wave input
Eth
16.67
2.5
100
inf
ns
7
EXTAL input low1
(40% to 60% duty cycle)
Crystal oscillator
Square wave input
Etl
16.67
2.5
100
inf
ns
8
EXTAL cycle time
With PLL disabled
With PLL enabled
Etc
5
33.3
inf
500
ns
9
Instruction cycle time
With PLL disabled
With PLL enabled
Tc
5
44
inf
5120
ns
Note:
1. Measured at 50% of the input transition.
2. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time
required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock
frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low
time requirements are met.
3. Maximum frequency of 200 MHz supported at 0.95 V < VVDD_CORE < 1.05 V and –40 < Tj < 100° C
Maximum frequency of 250 MHz supported at 1.14 V < VVDD_CORE < 1.26 V and 0 < Tj < 90° C
4. PLLLOCK = 200 μs.
Table 7. Reset, Stop, Mode Select, and Interrupt Timing
No.
Characteristics
Expression
Min
Max
Unit
10
Delay from RESET assertion to all pins at reset value3
——
11
ns
11
Required RESET duration4
Power on, external clock generator, PLL disabled
Power on, external clock generator, PLL enabled
2
× TC
10
—
ns
2
× TC
10
—
ns
13
Syn reset deassert delay time
Minimum
2
× TC
10
—
ns
Maximum (PLL enabled)
(2xTC)+PLLLOCK
200
—
us
14
Mode select setup time
—
10
—
ns
15
Mode select hold time
—
12
—
ns
16
Minimum edge-triggered interrupt request assertion width
—
7
—
ns
17
Minimum edge-triggered interrupt request deassertion width
—
4
—
ns
18
Delay from interrupt trigger to interrupt code execution
10
× TC + 4
54
—
ns
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