參數(shù)資料
型號(hào): DSPIC30F6010-20E/PF
廠商: Microchip Technology
文件頁(yè)數(shù): 39/110頁(yè)
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 144K 80TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 90
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: 高級(jí)欠壓探測(cè)/復(fù)位,LVD,電機(jī)控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 68
程序存儲(chǔ)器容量: 144KB(48K x 24)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 80-TQFP
包裝: 托盤
配用: DM300019-ND - BOARD DEMO DSPICDEM 80L STARTER
AC164314-ND - MODULE SKT FOR PM3 80PF
DM300020-ND - BOARD DEV DSPICDEM MC1 MOTORCTRL
其它名稱: DSPIC30F601020EPF
dsPIC30F6010
DS70119E-page 32
2006 Microchip Technology Inc.
4.1.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP Accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU instruc-
tions, Move and Accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
In summary, the following addressing modes are
supported by Move and Accumulator instructions:
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
4.1.4
MAC
INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC
and MSC), also
referred to as MAC instructions, utilize a simplified set of
addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.
The two source operand prefetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU and W10 and W11 will always be directed to the
Y AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9 and Y data space
for W10 and W11.
In summary, the following addressing modes are
supported by the MAC class of instructions:
Register Indirect
Register Indirect Post-Modified by 2
Register Indirect Post-Modified by 4
Register Indirect Post-Modified by 6
Register Indirect with Register Offset (Indexed)
4.1.5
OTHER INSTRUCTIONS
Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
4.2
Modulo Addressing
Modulo Addressing is a method of providing an auto-
mated means to support circular data buffers using
hardware. The objective is to remove the need for soft-
ware to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.
Modulo Addressing can operate in either data or pro-
gram space (since the data pointer mechanism is essen-
tially the same for both). One circular buffer can be
supported in each of the X (which also provides the
pointers into Program space) and Y data spaces. Mod-
ulo Addressing can operate on any W register pointer.
However, it is not advisable to use W14 or W15 for Mod-
ulo Addressing, since these two registers are used as
the Stack Frame Pointer and Stack Pointer, respectively.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are cer-
tain restrictions on the buffer start address (for incre-
menting buffers) or end address (for decrementing
buffers) based upon the direction of the buffer.
The only exception to the usage restrictions is for buff-
ers which have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bidirectional mode, (i.e., address bound-
ary checks will be performed on both the lower and
upper address boundaries).
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA. How-
ever, the 4-bit Wb (Register Offset) field is
shared
between
both
source
and
destination (but typically only used by
one).
Note:
Not all instructions support all the address-
ing
modes
given
above.
Individual
instructions may support different subsets
of these addressing modes.
Note:
Register Indirect with Register Offset
Addressing is only available for W9 (in X
space) and W11 (in Y space).
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