參數(shù)資料
型號: DSPIC30F6010-20E/PF
廠商: Microchip Technology
文件頁數(shù): 52/110頁
文件大小: 0K
描述: IC DSPIC MCU/DSP 144K 80TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 90
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: 高級欠壓探測/復(fù)位,LVD,電機控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 68
程序存儲器容量: 144KB(48K x 24)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 80-TQFP
包裝: 托盤
配用: DM300019-ND - BOARD DEMO DSPICDEM 80L STARTER
AC164314-ND - MODULE SKT FOR PM3 80PF
DM300020-ND - BOARD DEV DSPICDEM MC1 MOTORCTRL
其它名稱: DSPIC30F601020EPF
dsPIC30F6010
DS70119E-page 44
2006 Microchip Technology Inc.
6.4
RTSP Operation
The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instruc-
tions, or 96 bytes. Each panel consists of 128 rows, or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program 32
instructions at one time.
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches; instruction 0, instruction 1,
etc. The addresses loaded must always be from an
even group of 32 boundary.
The basic sequence for RTSP programming is to set up
a table pointer, then do a series of TBLWT instructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register. 32
TBLWTL
and 32 TBLWTH instructions are required to
load the 32 instructions.
All of the table write operations are single word writes
(2 instruction cycles), because only the table latches
are written.
After the latches are written, a programming operation
needs to be initiated to program the data.
The Flash Program Memory is readable, writable and
erasable during normal operation over the entire VDD
range.
6.5
RTSP Control Registers
The four SFRs used to read and write the program
Flash memory are:
NVMCON
NVMADR
NVMADRU
NVMKEY
6.5.1
NVMCON REGISTER
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed, and
start of the programming cycle.
6.5.2
NVMADR REGISTER
The NVMADR register is used to hold the lower two
bytes of the effective address. The NVMADR register
captures the EA<15:0> of the last table instruction that
has been executed and selects the row to write.
6.5.3
NVMADRU REGISTER
The NVMADRU register is used to hold the upper byte
of the effective address. The NVMADRU register cap-
tures the EA<23:16> of the last table instruction that
has been executed.
6.5.4
NVMKEY REGISTER
NVMKEY is a write-only register that is used for write
protection. To start a programming or an erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 6.6
“Programming Operations” for further details.
Note:
The user can also directly write to the
NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.
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