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參數(shù)資料
型號(hào)： DSPIC30F6010-20E/PF
廠商： Microchip Technology
文件頁(yè)數(shù)： 58/110頁(yè)
文件大小： 0K
描述： IC DSPIC MCU/DSP 144K 80TQFP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 90
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 20 MIPS
連通性： CAN，I²C，SPI，UART/USART
外圍設(shè)備： 高級(jí)欠壓探測(cè)/復(fù)位，LVD，電機(jī)控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 68
程序存儲(chǔ)器容量： 144KB（48K x 24）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 4K x 8
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-TQFP
包裝： 托盤(pán)
配用： DM300019-ND - BOARD DEMO DSPICDEM 80L STARTER
AC164314-ND - MODULE SKT FOR PM3 80PF
DM300020-ND - BOARD DEV DSPICDEM MC1 MOTORCTRL
其它名稱： DSPIC30F601020EPF
2006 Microchip Technology Inc.
DS70119E-page 49
dsPIC30F6010
7.0
DATA EEPROM MEMORY
The Data EEPROM Memory is readable and writable
during normal operation over the entire VDD range. The
data EEPROM memory is directly mapped in the
program memory address space.
The four SFRs used to read and write the program
Flash memory are used to access data EEPROM
memory, as well. As described in Section 4.0, these
registers are:
NVMCON
NVMADR
NVMADRU
NVMKEY
The EEPROM data memory allows read and write of
single words and 16-word blocks. When interfacing to
data memory, NVMADR, in conjunction with the
NVMADRU register, is used to address the EEPROM
location being accessed. TBLRDL and TBLWTL instruc-
tions are used to read and write data EEPROM. The
dsPIC30F6010 device has 8 Kbytes (4K words) of data
EEPROM, with an address range from 0x7FF000 to
0x7FFFFE.
A word write operation should be preceded by an erase
of the corresponding memory location(s). The write
typically requires 2 ms to complete, but the write time
will vary with voltage and temperature.
A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is respon-
sible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operation. Attempting to read the data EEPROM while
a programming or erase operation is in progress results
in unspecified data.
Control bit WR initiates write operations, similar to pro-
gram Flash writes. This bit cannot be cleared, only set,
in software. This bit is cleared in hardware at the com-
pletion of the write operation. The inability to clear the
WR bit in software prevents the accidental or
premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset, during normal oper-
ation. In these situations, following Reset, the user can
check the WRERR bit and rewrite the location. The
address register NVMADR remains unchanged.
7.1
Reading the Data EEPROM
A TBLRD instruction reads a word at the current pro-
gram word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in
register W4, as shown in Example 7-1.
EXAMPLE 7-1:
DATA EEPROM READ
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Note:
Interrupt flag bit NVMIF in the IFS0 regis-
ter is set when write is complete. It must be
cleared in software.
MOV
#LOW_ADDR_WORD,W0
; Init Pointer
MOV
#HIGH_ADDR_WORD,W1
MOV
W1,TBLPAG
TBLRDL
[ W0 ], W4
; read data EEPROM
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