參數(shù)資料
型號(hào)： DSPIC30F6010-20E/PF
廠商： Microchip Technology
文件頁數(shù)： 47/110頁
文件大小： 0K
描述： IC DSPIC MCU/DSP 144K 80TQFP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 90
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 20 MIPS
連通性： CAN，I²C，SPI，UART/USART
外圍設(shè)備： 高級(jí)欠壓探測/復(fù)位，LVD，電機(jī)控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 68
程序存儲(chǔ)器容量： 144KB（48K x 24）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-TQFP
包裝： 托盤
配用： DM300019-ND - BOARD DEMO DSPICDEM 80L STARTER
AC164314-ND - MODULE SKT FOR PM3 80PF
DM300020-ND - BOARD DEV DSPICDEM MC1 MOTORCTRL
其它名稱： DSPIC30F601020EPF
2006 Microchip Technology Inc.
DS70119E-page 39
dsPIC30F6010
5.2
Reset Sequence
A Reset is not a true exception, because the interrupt
controller is not involved in the Reset process. The pro-
cessor initializes its registers in response to a Reset,
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory loca-
tion, immediately followed by the address target for the
GOTO
instruction. The processor executes the GOTO to
the specified address and then begins operation at the
specified target (start) address.
5.2.1
RESET SOURCES
There are 5 sources of error which will cause a device
Reset:
Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an address pointer will cause a Reset.
Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
Brown-out Reset (BOR):
A momentary dip in the power supply to the
device has been detected, which may result in
malfunction.
Trap Lockout:
Occurrence of multiple Trap conditions
simultaneously will cause a Reset.
5.3
Traps
Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority as shown in Figure 5-1. They
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
Note that many of these Trap conditions can only be
detected when they occur. Consequently, the question-
able instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
There are 8 fixed priority levels for traps: Level 8
through Level 15, which implies that the IPL3 is always
set during processing of a trap.
If the user is not currently executing a trap, and he sets
the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
5.3.1
TRAP SOURCES
The following traps are provided with increasing prior-
ity. However, since all traps can be nested, priority has
little effect.
Math Error Trap:
The math error trap executes under the following four
circumstances:
1.
Should an attempt be made to divide by zero,
the divide operation will be aborted on a cycle
boundary and the trap taken.
2.
If enabled, a math error trap will be taken when
an arithmetic operation on either accumulator A
or B causes an overflow from bit 31 and the
Accumulator Guard bits are not utilized.
3.
If enabled, a math error trap will be taken when
an arithmetic operation on either accumulator A
or B causes a catastrophic overflow from bit 39
and all saturation is disabled.
4.
If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap will occur.
Note:
If the user does not intend to take correc-
tive action in the event of a trap error
condition, these vectors must be loaded
with the address of a default handler that
simply contains the RESET instruction. If,
on the other hand, one of the vectors
containing an invalid address is called, an
address error trap is generated.
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DSPIC30F6010-20I/PF 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 20MHz 144KB Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSPIC30F6010-20I/PF 制造商:Microchip Technology Inc 功能描述:16BIT 20MIPS DSPIC SMD 30F6010
DSPIC30F6010-30I/PF 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 30MHz 144KB Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSPIC30F6010-30I/PF 制造商:Microchip Technology Inc 功能描述:16BIT 30MIPS DSPIC SMD 30F6010
DSPIC30F6010-30I/PF 制造商:Microchip Technology Inc 功能描述:Digital Signal Processor IC Frequency Ma
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