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參數(shù)資料
| 型號(hào)： | DSPIC30F6010-20E/PF |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 6/110頁 |
| 文件大小： | 0K |
| 描述： | IC DSPIC MCU/DSP 144K 80TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | dsPIC™ 30F |
| 核心處理器： | dsPIC |
| 芯體尺寸： | 16-位 |
| 速度： | 20 MIPS |
| 連通性： | CAN，I²C，SPI，UART/USART |
| 外圍設(shè)備： | 高級(jí)欠壓探測/復(fù)位，LVD，電機(jī)控制 PWM，QEI，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 68 |
| 程序存儲(chǔ)器容量： | 144KB（48K x 24） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-TQFP |
| 包裝： | 托盤 |
| 配用： | DM300019-ND - BOARD DEMO DSPICDEM 80L STARTER AC164314-ND - MODULE SKT FOR PM3 80PF DM300020-ND - BOARD DEV DSPICDEM MC1 MOTORCTRL |
| 其它名稱： | DSPIC30F601020EPF |
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2006 Microchip Technology Inc.
DS70119E-page 101
dsPIC30F6010
17.2
I2C Module Addresses
The I2CADD register contains the Slave mode
addresses. The register is a 10-bit register. If the A10M
bit (I2CCON<10>) is ‘0’, the address is interpreted by
the module as a 7-bit address. When an address is
received, it is compared to the 7 LSbs of the I2CADD
register.
If the A10M bit is 1, the address is assumed to be a 10-
bit address. When an address is received, it will be
compared with the binary value ‘1 1 1 1 0 A9 A8’
(where A9, A8 are two Most Significant bits of
I2CADD). If that value matches, the next address will
be compared with the Least Significant 8 bits of
I2CADD, as specified in the 10-bit addressing protocol.
Table 17-1 lists the Slave addresses supported by
dsPIC30F devices.
17.3
I2C 7-bit Slave Mode Operation
Once enabled (I2CEN = 1), the slave module waits for
a Start bit to occur (i.e., the I2C module is ‘Idle’). Follow-
ing the detection of a Start bit, 8 bits are shifted into
I2CRSR and the address is compared against
I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>
are compared against I2CRSR<7:1> and I2CRSR<0>
is the R_W bit. All incoming bits are sampled on the ris-
ing edge of SCL.
If an address match occurs, an acknowledgement is
sent, and the slave event interrupt flag (SI2CIF) is set
on the falling edge of the ninth (ACK) bit. The address
match does not affect the contents of the I2CRCV
buffer or the RBF bit.
17.3.1
SLAVE TRANSMISSION
If the R_W bit received is a ‘1’, the serial port goes into
Transmit mode. It sends an ACK on the ninth bit and
then holds SCL to ‘0’ until the CPU responds by writing
to I2CTRN. SCL is released by setting the SCLREL bit,
and 8 bits of data are shifted out. Data bits are shifted
out on the falling edge of SCL, such that SDA is valid
during SCL high (see timing diagram). The interrupt
pulse is sent on the falling edge of the ninth clock pulse,
regardless of the status of the ACK received from the
master.
17.3.2
SLAVE RECEPTION
If the R_W bit received is a ‘0’ during an address
match, Receive mode is initiated. Incoming bits are
sampled on the rising edge of SCL. After 8 bits are
received, if I2CRCV is not full or I2COV is not set,
I2CRSR is transferred to I2CRCV. ACK is sent on the
ninth clock.
If the RBF flag is set, indicating that I2CRCV is still
holding data from a previous operation (RBF = 1), the
ACK is not sent; however, the interrupt pulse is gener-
ated. In the case of an overflow, the contents of the
I2CRSR are not loaded into the I2CRCV.
17.4
I2C 10-bit Slave Mode Operation
In 10-bit mode, the basic receive and transmit opera-
tions are the same as in the 7-bit mode. However, the
criteria for address match is more complex.
The I2C specification dictates that a slave must be
addressed for a write operation, with two address bytes
following a Start bit.
The A10M bit is a control bit that signifies that the
address in I2CADD is a 10-bit address rather than a
7-bit address. The address detection protocol for the
first byte of a message address is identical for 7-bit
and 10-bit messages, but the bits being compared are
different.
I2CADD holds the entire 10-bit address. Upon receiv-
ing an address following a Start bit, I2CRSR <7:3> is
compared against a literal ‘11110’ (the default 10-bit
address) and I2CRSR<2:1> are compared against
I2CADD<9:8>. If a match occurs, and if R_W = 0, the
interrupt pulse is sent. The ADD10 bit is cleared to indi-
cate a partial address match. If a match fails or R_W =
1
, the ADD10 bit is cleared and the module returns to
the Idle state.
The low byte of the address is then received and com-
pared with I2CADD<7:0>. If an address match occurs,
the interrupt pulse is generated and the ADD10 bit is
set, indicating a complete 10-bit address match. If an
address match did not occur, the ADD10 bit is cleared
and the module returns to the Idle state.
17.4.1
10-BIT MODE SLAVE
TRANSMISSION
Once a slave is addressed in this fashion, with the full
10-bit
address
(we
refer
to
this
state
as
"PRIOR_ADDR_MATCH"), the master can begin send-
ing data bytes for a slave reception operation.
TABLE 17-1:
7-BIT I2C SLAVE
ADDRESSES SUPPORTED BY
dsPIC30F
0x00
General call address or Start byte
0x01-0x03
Reserved
0x04-0x07
Hs mode Master codes
0x08-0x77
Valid 7-bit addresses
0x78-0x7b
Valid 10-bit addresses (lower 7 bits)
0x7c-0x7f
Reserved
Note:
The I2CRCV is loaded if the I2COV bit = 1
and the RBF flag = 0. In this case, a read
of the I2CRCV was performed, but the
user did not clear the state of the I2COV
bit before the next receive occurred. The
acknowledgement is not sent (ACK = 1)
and the I2CRCV is updated.
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| DSPIC30F6010-20I/PF | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 20MHz 144KB Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSPIC30F6010-20I/PF | 制造商:Microchip Technology Inc 功能描述:16BIT 20MIPS DSPIC SMD 30F6010 |
| DSPIC30F6010-30I/PF | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 30MHz 144KB Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSPIC30F6010-30I/PF | 制造商:Microchip Technology Inc 功能描述:16BIT 30MIPS DSPIC SMD 30F6010 |
| DSPIC30F6010-30I/PF | 制造商:Microchip Technology Inc 功能描述:Digital Signal Processor IC Frequency Ma |
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