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參數(shù)資料
| 型號(hào)： | EDD51321CBH-6CTT-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits DDR SDRAM |
| 中文描述： | 16M X 32 SYNCHRONOUS DRAM, 5 ns, PBGA90 |
| 封裝： | ROHS COMPLIANT, FBGA-90 |
| 文件頁數(shù)： | 11/55頁 |
| 文件大?。?/td> | 589K |
| 代理商： | EDD51321CBH-6CTT-E |
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EDD51321CBH
Preliminary Data Sheet E1094E30 (Ver. 3.0)
11
Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross
point of the CK rising edge and the /CK falling edge. When a read operation, DQSs and DQs are referred to the
cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS
and the VDDQ/2 level. DQSs for write operation are referred to the cross point of the CK and the /CK. The other
input signals are referred at CK rising edge.
/CS (input pin)
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address is loaded via the A0 to the A8 at the cross point
of the CK rising edge and the /CK falling edge in a read or a write command cycle (See “Address Pins Table”). This
column address becomes the starting address of a burst operation.
[Address Pins Table]
Address (A0 to A12)
Part number
Page size
Organization
Row address
Column address
EDD51321CBH
2KB
×
32 bits
AX0 to AX12
AY0 to AY8
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = high when read or write
command, auto precharge function is enabled.
BA0 and BA1 (input pins)
BA0 and BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3.
(See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD51321CBH-7ETT-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD51321DBH-5BTS-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR Mobile RAM? WTR (Wide Temperature Range) |
| EDD51321DBH-6ETS-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR Mobile RAM? WTR (Wide Temperature Range) |
| EDD51321DBH-TS | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR Mobile RAM? WTR (Wide Temperature Range) |
| EDD51323DBH-5BLS-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR Mobile RAM? WTR (Wide Temperature Range), Low Power Function |
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