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參數(shù)資料
| 型號： | EDD51321CBH-6CTT-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits DDR SDRAM |
| 中文描述： | 16M X 32 SYNCHRONOUS DRAM, 5 ns, PBGA90 |
| 封裝： | ROHS COMPLIANT, FBGA-90 |
| 文件頁數(shù)： | 20/55頁 |
| 文件大?。?/td> | 589K |
| 代理商： | EDD51321CBH-6CTT-E |
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EDD51321CBH
Preliminary Data Sheet E1094E30 (Ver. 3.0)
20
Operation of the DDR SDRAM
Initialization
The DDR SDRAM is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 200
μ
s or longer pause must precede any signal toggling.
VDD should be turned on simultaneously or before VDDQ.
(2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3) Once the precharge is completed and the minimum tRP is satisfied, two or more Auto-refresh must be performed.
(4) Both the mode register and the extended mode register must be programmed. After the mode register set cycle
or the extended mode register set cycle, tMRD (2 clocks minimum) pause must be satisfied.
Remarks:
1 The sequence of Auto-refresh, mode register programming and extended mode register programming above may
be transposed.
2
CKE must be held high.
Mode Register and Extended Mode Register Set
There are two mode registers, the mode register and the extended mode register so as to define the operating
mode. Parameters are set to both through the A0 to the A12 and BA0 and BA1 pins by the mode register set
command [MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode
register are set by inputting signal via the A0 to the A12 and BA0 and BA1 pins during mode register set cycles.
BA0 and BA1 determine which one of the mode register or the extended mode register are set. Prior to a read or a
write operation, the mode register must be set.
Mode register
The mode register has four fields;
Reserved
/CAS latency
Wrap type
Burst length
Following mode register programming, no command can be issued before at least 2 clocks have elapsed.
/CAS Latency
/CAS latency must be set to 3.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become high-Z. The burst length is programmable as 2, 4 and 8.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed.
This order is programmable as either
“Sequential” or “Interleave”. “Burst Operation” shows the addressing sequence for each burst length for each wrap
type.
: A12 through A7
: A6 through A4
: A3
: A2 through A0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD51321CBH-7ETT-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD51321DBH-5BTS-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR Mobile RAM? WTR (Wide Temperature Range) |
| EDD51321DBH-6ETS-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR Mobile RAM? WTR (Wide Temperature Range) |
| EDD51321DBH-TS | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR Mobile RAM? WTR (Wide Temperature Range) |
| EDD51323DBH-5BLS-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR Mobile RAM? WTR (Wide Temperature Range), Low Power Function |
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