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參數(shù)資料
| 型號(hào)： | EDD51321CBH-6CTT-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 512M bits DDR SDRAM |
| 中文描述： | 16M X 32 SYNCHRONOUS DRAM, 5 ns, PBGA90 |
| 封裝： | ROHS COMPLIANT, FBGA-90 |
| 文件頁(yè)數(shù)： | 18/55頁(yè) |
| 文件大小： | 589K |
| 代理商： | EDD51321CBH-6CTT-E |
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EDD51321CBH
Preliminary Data Sheet E1094E30 (Ver. 3.0)
18
CKE Truth Table
CKE
Current state
Command
n – 1
n
/CS
/RAS
/CAS
/WE
Address
Notes
Idle
Auto-refresh command (REF)
H
H
L
L
L
H
×
2
Idle
Self-refresh entry (SELF)
H
L
L
L
L
H
×
2
H
L
L
H
H
H
×
Active/Idle
Power-down entry (PDEN)
H
L
H
×
×
×
×
L
H
L
H
H
H
×
Self-refresh
Self-refresh exit (SELFX)
L
H
H
×
×
×
×
L
H
L
H
H
H
×
Power-down
Power-down exit (PDEX)
L
H
H
×
×
×
×
Notes: 1. H: VIH
. L: VIL
×
: Don’t care.
2. All the banks must be in IDLE before executing this command.
3. The CKE level must be kept for 1 clock cycle at least.
Auto-refresh command [REF]
This command executes auto-refresh. The bank and the ROW addresses to be refreshed are internally determined
by the internal refresh controller. The output buffer becomes high-Z after auto-refresh start. Precharge has been
completed automatically after the auto-refresh. The ACT or MRS command can be issued tRFC
after the last auto-
refresh command.
The average refresh cycle is 7.8
μ
s. To allow for improved efficiency in scheduling, some flexibility in the absolute
refresh interval (64ms) is provided. A maximum of eight auto-refresh commands can be posted to the DDR SDRAM
or the maximum absolute interval between any auto-refresh command and the next auto-refresh command is
8
×
tREF.
Self-refresh entry [SELF]
This command starts self-refresh. The self-refresh operation continues as long as CKE is held low. During the self-
refresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is
terminated by a self-refresh exit command.
Power-down mode entry [PDEN]
tPDEN after the cycle when [PDEN] is issued, the DDR SDRAM enters into power-down mode. In power-down
mode, power consumption is suppressed by deactivating the input initial circuit. Power-down mode continues while
CKE is held low. No internal refresh operation occurs during the power-down mode.
Self-refresh exit [SELFX]
This command is executed to exit from self-refresh mode. tSREX after [SELFX], the device will be into idle state.
Power-down exit [PDEX]
The DDR SDRAM can exit from power-down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.
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| EDD51321CBH-7ETT-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
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| EDD51323DBH-5BLS-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR Mobile RAM? WTR (Wide Temperature Range), Low Power Function |
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