參數(shù)資料
型號: EDD51321CBH-6CTT-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 512M bits DDR SDRAM
中文描述: 16M X 32 SYNCHRONOUS DRAM, 5 ns, PBGA90
封裝: ROHS COMPLIANT, FBGA-90
文件頁數(shù): 27/55頁
文件大?。?/td> 589K
代理商: EDD51321CBH-6CTT-E
EDD51321CBH
Preliminary Data Sheet E1094E30 (Ver. 3.0)
27
Auto Precharge
Read with auto precharge
The precharge is automatically performed after completing a read operation. The precharge starts BL/2 (= tRPD)
clocks after READA command input.
tRAS lock out mechanism for READA allows a read command with auto
precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min)
specification. A column command to the other active bank can be issued the next cycle after the last data output.
Read with auto precharge command does not limit row commands execution for other bank.
out0
out1
out2
out3
CK
/CK
DQ
Command
tRP (min)
tRCD (min)
ACT
Note: Internal auto-precharge starts at the timing indicated by " ".
NOP
BL/2 (= tRPD)
READA
ACT
DQS
tAC,tDQSCK
tRAS (min)
Read with auto precharge
Write with auto precharge
The precharge is automatically performed after completing a burst write operation. The precharge operation is
started Write latency (WL) + BL/2 + tWR (= tWPD) clocks after WRITA command issued.
A column command to the other banks can be issued the next cycle after the internal precharge command issued.
Write with auto precharge command does not limit row commands execution for other bank.
in1
in2
in3
in4
CK
/CK
DQ
Command
DM
tRAS (min)
tRCD (min)
tRP
DQS
ACT
WRITA
ACT
WL + BL/2 + tWR (= tWPD)
Note: Internal auto-precharge starts at the timing indicated by " ".
BL = 4
NOP
NOP
Burst Write (BL = 4)
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