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參數(shù)資料
| 型號： | EDD51321CBH-6CTT-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits DDR SDRAM |
| 中文描述： | 16M X 32 SYNCHRONOUS DRAM, 5 ns, PBGA90 |
| 封裝： | ROHS COMPLIANT, FBGA-90 |
| 文件頁數(shù)： | 24/55頁 |
| 文件大?。?/td> | 589K |
| 代理商： | EDD51321CBH-6CTT-E |
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EDD51321CBH
Preliminary Data Sheet E1094E30 (Ver. 3.0)
24
Read/Write Operations
Bank Active
A read or a write operation begins with the bank active command [ACT]. The bank active command determines a
bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after
the ACT is issued.
Read operation
The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read
command is issued. The burst length (BL) determines the length of a sequential output data by the read command
that can be set to 2, 4 or 8. The starting address of the burst read is defined by the column address, the bank select
address (See “Pin Function”) in the cycle when the read command is issued. The data output timing is characterized
by CL and tAC. The read burst start (CL-1)
×
tCK + tAC (ns) after the clock rising edge where the read command is
latched. The DDR SDRAM outputs the data strobe through DQS pins simultaneously with data. tRPRE prior to the
first rising edge of the data strobe, the DQS pins are driven low from high-Z state. This low period of DQS is referred
as read preamble. The burst data are output coincidentally at both the rising and falling edge of the data strobe.
The DQ pins become high-Z in the next cycle after the burst read operation completed. tRPST from the last falling
edge of the data strobe, the DQS pins become high-Z. This low period of DQS is referred as read postamble.
out0 out1
out0 out1 out2 out3
out0 out1 out2 out3 out4 out5 out6 out7
CK
/CK
Address
DQS
DQ
BL = 2
BL = 4
BL = 8
Command
CL = 3
BL: Burst length
tRCD
tRPST
ACT
NOP
NOP
NOP
READ
Row
Column
tRPRE
Read Operation (Burst Length)
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|---|---|
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| EDE1104ABSE | 1G bits DDR2 SDRAM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EDD51321CBH-7ETT-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD51321DBH-5BTS-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR Mobile RAM? WTR (Wide Temperature Range) |
| EDD51321DBH-6ETS-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR Mobile RAM? WTR (Wide Temperature Range) |
| EDD51321DBH-TS | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR Mobile RAM? WTR (Wide Temperature Range) |
| EDD51323DBH-5BLS-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR Mobile RAM? WTR (Wide Temperature Range), Low Power Function |
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