參數(shù)資料
型號: EDD51321CBH-6CTT-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 512M bits DDR SDRAM
中文描述: 16M X 32 SYNCHRONOUS DRAM, 5 ns, PBGA90
封裝: ROHS COMPLIANT, FBGA-90
文件頁數(shù): 28/55頁
文件大?。?/td> 589K
代理商: EDD51321CBH-6CTT-E
EDD51321CBH
Preliminary Data Sheet E1094E30 (Ver. 3.0)
28
Command Intervals
A Read command to the consecutive Read command Interval
Destination row of the
consecutive read command
Bank
address
Row address State
Operation
1. Same
Same
ACTIVE
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank without interrupting the preceding read operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive read command can be issued.
2. Same
Different
3. Different
Any
ACTIVE
IDLE
out
A0
out
A1
out
B0
out
B1
out
B2
out
B3
CK
/CK
Address
BA
DQ
DQS
Command
tn
t0
tn+1
tn+2
tn+3
tn+4
tn+5
tn+6
Bank0
Active
CL = 3
BL = 4
Bank0
NOP
ACT
NOP
READ
Row
READ
Column = A
Read
Column = B
Read
Column = A
Dout
Column = B
Dout
Column A
Column B
READ to READ Command Interval (same ROW address in the same bank)*
Note: n
4
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