參數(shù)資料
型號(hào): EDD51321CBH-6CTT-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 512M bits DDR SDRAM
中文描述: 16M X 32 SYNCHRONOUS DRAM, 5 ns, PBGA90
封裝: ROHS COMPLIANT, FBGA-90
文件頁(yè)數(shù): 39/55頁(yè)
文件大?。?/td> 589K
代理商: EDD51321CBH-6CTT-E
EDD51321CBH
Preliminary Data Sheet E1094E30 (Ver. 3.0)
39
A Write command to the consecutive Precharge command interval (same bank)
Operation by each case of destination bank of the consecutive Precharge command.
Bank address
Operation
1.
Same
The PRE and PALL command can interrupt a write operation.
To complete a burst write operation, tWPD is required between the write and the precharge
command. Please refer to the following timing chart.
The PRE command does not interrupt a write command.
No interval timing is required between the write and the precharge command.
2.
Different
WRITE to PRECHARGE Command Interval (same bank)
The minimum interval tWPD is necessary between the write command and the precharge command.
in0
in1
in2
in3
CK
/CK
DQ
DM
DQS
Command
t1
t0
t2
t3
t4
tn
tn + 1
tn + 2
Last data input
tWPD
WRIT
NOP
NOP
tWR
PRE/PALL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4)
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