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型號(hào)：	EP2S30F672I4N
廠商：	Altera
文件頁(yè)數(shù)：	190/768頁(yè)
文件大?。?/td>	0K
描述：	IC STRATIX II FPGA 30K 672-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝：	10
系列：	Stratix® II
LAB/CLB數(shù)：	1694
邏輯元件/單元數(shù)：	33880
RAM 位總計(jì)：	1369728
輸入/輸出數(shù)：	500
電源電壓：	1.15 V ~ 1.25 V
安裝類型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	672-BBGA
供應(yīng)商設(shè)備封裝：	672-BGA（27x27）
其它名稱：	544-1900 EP2S30F672I4N-ND

Altera Corporation

May 2007

Stratix II Device Handbook, Volume 1

Stratix II Architecture

One ALM contains two programmable registers. Each register has data,

clock, clock enable, synchronous and asynchronous clear, asynchronous

load data, and synchronous and asynchronous load/preset inputs.

Global signals, general-purpose I/O pins, or any internal logic can drive

the register's clock and clear control signals. Either general-purpose I/O

pins or internal logic can drive the clock enable, preset, asynchronous

load, and asynchronous load data. The asynchronous load data input

comes from the datae or dataf input of the ALM, which are the same

inputs that can be used for register packing. For combinational functions,

the register is bypassed and the output of the LUT drives directly to the

outputs of the ALM.

Each ALM has two sets of outputs that drive the local, row, and column

routing resources. The LUT, adder, or register output can drive these

output drivers independently (see Figure 2–6). For each set of output

drivers, two ALM outputs can drive column, row, or direct link routing

connections, and one of these ALM outputs can also drive local

interconnect resources. This allows the LUT or adder to drive one output

while the register drives another output. This feature, called register

packing, improves device utilization because the device can use the

special packing mode allows the register output to feed back into the LUT

of the same ALM so that the register is packed with its own fan-out LUT.

This provides another mechanism for improved fitting. The ALM can also

drive out registered and unregistered versions of the LUT or adder

See the Performance & Logic Efficiency Analysis of Stratix II Devices White

Paper for more information on the efficiencies of the Stratix II ALM and

comparisons with previous architectures.

ALM Operating Modes

The Stratix II ALM can operate in one of the following modes:

Extended LUT mode

Arithmetic mode

Shared arithmetic mode

Each mode uses ALM resources differently. In each mode, eleven

available inputs to the ALM--the eight data inputs from the LAB local

interconnect; carry-in from the previous ALM or LAB; the shared

arithmetic chain connection from the previous ALM or LAB; and the

implement the desired logic function. LAB-wide signals provide clock,

asynchronous clear, asynchronous preset/load, synchronous clear,

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