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型號(hào)：	EP2S30F672I4N
廠商：	Altera
文件頁(yè)數(shù)：	373/768頁(yè)
文件大小：	0K
描述：	IC STRATIX II FPGA 30K 672-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝：	10
系列：	Stratix® II
LAB/CLB數(shù)：	1694
邏輯元件/單元數(shù)：	33880
RAM 位總計(jì)：	1369728
輸入/輸出數(shù)：	500
電源電壓：	1.15 V ~ 1.25 V
安裝類型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	672-BBGA
供應(yīng)商設(shè)備封裝：	672-BGA（27x27）
其它名稱：	544-1900 EP2S30F672I4N-ND

Altera Corporation

Stratix II Device Handbook, Volume 2

January 2008

Enhancements In Stratix II and Stratix II GX Devices

When using the Stratix II and Stratix II GX top and bottom I/O banks

(I/O banks 3, 4, 7, or 8) to interface with a DDR memory, at least one PLL

with two outputs is needed to generate the system clock and the write

clock. The system clock generates the DQS write signals, commands, and

addresses. The write clock is either shifted by –90° or 90° from the system

clock and is used to generate the DQ signals during writes.

For DDR and DDR2 SDRAM interfaces above 200 MHz, Altera also

recommends a second read PLL to help ease resynchronization.

When using the Stratix II and Stratix II GX side I/O banks 1, 2, 5, or 6 to

interface with DDR SDRAM devices, two PLLs may be needed per I/O

bank for best performance. Since the side I/O banks do not have

dedicated circuitry, one PLL captures data from the DDR SDRAM and

another PLL generates the write signals, commands, and addresses to the

DDR SDRAM device. Stratix II and Stratix II GX side I/O banks can

support DDR SDRAM up to 150 MHz.

Enhancements

In Stratix II and

Stratix II GX

Stratix II and Stratix II GX external memory interfaces support differs

from Stratix external memory interfaces support in the following ways:

A PLL output can now be used as the input reference clock to the

The shifted DQS signal can now go into the logic array.

The DLL in Stratix II and Stratix II GX devices has more phase-shift

options than in Stratix devices. It also has the option to add phase

offset settings.

Stratix II and Stratix II GX devices have DQS logic blocks with each

DQS pin that helps with fine tuning the phase shift.

The DQS delay settings can be routed from the DLL into the logic

array. You can also bypass the DLL and send the DQS delay settings

from the logic array to the DQS logic block.

Stratix II and Stratix II GX devices support DQSn pins.

The DQS/DQ groups now support ×4, ×9, ×18, and ×36 bus modes.

The DQS pins have been enhanced with the DQS postamble circuitry.

Conclusion

Stratix II and Stratix II GX devices support SDR SDRAM, DDR SDRAM,

DDR2 SDRAM, RLDRAM II, and QDRII SRAM external memories.

Stratix II and Stratix II GX devices feature high-speed interfaces that

transfer data between external memory devices at up to 300 MHz/600

Mbps. DQS phase-shift circuitry and DQS logic blocks within the

Stratix II and Stratix II GX devices allow you to fine-tune the phase shifts

for the input clocks or strobes to properly align clock edges as needed to

capture data.

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