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型號(hào)：	EP2S30F672I4N
廠商：	Altera
文件頁(yè)數(shù)：	641/768頁(yè)
文件大?。?/td>	0K
描述：	IC STRATIX II FPGA 30K 672-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝：	10
系列：	Stratix® II
LAB/CLB數(shù)：	1694
邏輯元件/單元數(shù)：	33880
RAM 位總計(jì)：	1369728
輸入/輸出數(shù)：	500
電源電壓：	1.15 V ~ 1.25 V
安裝類(lèi)型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	672-BBGA
供應(yīng)商設(shè)備封裝：	672-BGA（27x27）
其它名稱(chēng)：	544-1900 EP2S30F672I4N-ND

Altera Corporation

Stratix II Device Handbook, Volume 2

January 2008

Dedicated Remote System Upgrade Circuitry

The remote system upgrade control and status registers are clocked by

the 10-MHz internal oscillator (the same oscillator that controls the user

watchdog timer). However, the remote system upgrade shift and update

registers are clocked by the user clock input (RU_CLK).

Remote System Upgrade Control Register

The remote system upgrade control register stores the application

configuration page address and user watchdog timer settings. The

control register functionality depends on the remote system upgrade

mode selection. In remote update mode, the control register page address

bits are set to all zeros (7'b0 = 0000_000) at power up in order to load

the factory configuration. However, in local update mode the control

select the application configuration. Additionally, the control register

cannot be updated in local update mode, whereas a factory configuration

in remote update mode has write access to this register.

The control register bit positions are shown in Figure 8–7 and defined in

Table 8–4. In the figure, the numbers show the bit position of a setting

within a register. For example, bit number 8 is the enable bit for the

watchdog timer.

Figure 8–7. Remote System Upgrade Control Register

Update register

This register contains data similar to that in the control register. However, it can only be

updated by the factory configuration by shifting data into the shift register and issuing an

update operation. When a reconfiguration cycle is triggered by the factory configuration, the

control register is updated with the contents of the update register. During a read in a factory

configuration, this register is read into the shift register.

Status register

This register is written to by the remote system upgrade circuitry on every reconfiguration to

record the cause of the reconfiguration. This information is used by the factory configuration

to determine the appropriate action following a reconfiguration. During a capture cycle, this

Table 8–3. Remote System Upgrade Registers (Part 2 of 2)

Register

Description

Wd_timer[11..0]

PGM[2..0] AnF

20 19 18 17 16 15 14 13 12 11 10

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