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型號(hào)：	EP2S30F672I4N
廠商：	Altera
文件頁(yè)數(shù)：	34/768頁(yè)
文件大?。?/td>	0K
描述：	IC STRATIX II FPGA 30K 672-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝：	10
系列：	Stratix® II
LAB/CLB數(shù)：	1694
邏輯元件/單元數(shù)：	33880
RAM 位總計(jì)：	1369728
輸入/輸出數(shù)：	500
電源電壓：	1.15 V ~ 1.25 V
安裝類型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	672-BBGA
供應(yīng)商設(shè)備封裝：	672-BGA（27x27）
其它名稱：	544-1900 EP2S30F672I4N-ND

Altera Corporation

May 2007

Stratix II Device Handbook, Volume 1

Configuration & Testing

Operating Modes

The Stratix II architecture uses SRAM configuration elements that require

configuration data to be loaded each time the circuit powers up. The

process of physically loading the SRAM data into the device is called

configuration. During initialization, which occurs immediately after

configuration, the device resets registers, enables I/O pins, and begins to

operate as a logic device. The I/O pins are tri-stated during power-up,

and before and during configuration. Together, the configuration and

initialization processes are called command mode. Normal device

operation is called user mode.

SRAM configuration elements allow Stratix II devices to be reconfigured

in-circuit by loading new configuration data into the device. With real-

time reconfiguration, the device is forced into command mode with a

device pin. The configuration process loads different configuration data,

reinitializes the device, and resumes user-mode operation. You can

perform in-field upgrades by distributing new configuration files either

within the system or remotely.

is a dedicated input pin used to select POR delay times of 12 ms

or 100 ms during power-up. When the PORSEL pin is connected to

ground, the POR time is 100 ms; when the PORSEL pin is connected to

VCC, the POR time is 12 ms.

The nIO PULLUP pin is a dedicated input that chooses whether the

internal pull-ups on the user I/O pins and dual-purpose configuration

I/O pins (nCSO, ASDO, DATA[7..0], nWS, nRS, RDYnBSY, nCS, CS,

, PGM[2..0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLR) are on or

off before and during configuration. A logic high (1.5, 1.8, 2.5, 3.3 V) turns

off the weak internal pull-ups, while a logic low turns them on.

Stratix II devices also offer a new power supply, VCCPD, which must be

connected to 3.3 V in order to power the 3.3-V/2.5-V buffer available on

the configuration input pins and JTAG pins. VCCPD applies to all the JTAG

input pins (TCK, TMS, TDI, and TRST) and the configuration input pins

when VCCSEL is connected to ground. See Table 3–4 for more information

on the pins affected by VCCSEL.

The VCCSEL pin allows the VCCIO setting (of the banks where the

configuration inputs reside) to be independent of the voltage required by

the configuration inputs. Therefore, when selecting the VCCIO, the VIL and

VIH levels driven to the configuration inputs do not have to be a concern.

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