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型號(hào)：	EP2S30F672I4N
廠商：	Altera
文件頁(yè)數(shù)：	647/768頁(yè)
文件大?。?/td>	0K
描述：	IC STRATIX II FPGA 30K 672-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝：	10
系列：	Stratix® II
LAB/CLB數(shù)：	1694
邏輯元件/單元數(shù)：	33880
RAM 位總計(jì)：	1369728
輸入/輸出數(shù)：	500
電源電壓：	1.15 V ~ 1.25 V
安裝類型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	672-BBGA
供應(yīng)商設(shè)備封裝：	672-BGA（27x27）
其它名稱：	544-1900 EP2S30F672I4N-ND

Altera Corporation

January 2008

Stratix II Device Handbook, Volume 2

Remote System Upgrades with Stratix II and Stratix II GX Devices

The user watchdog timer is disabled in factory configurations

and during the configuration cycle of the application

configuration. It is enabled after the application configuration

enters user mode.

Interface Signals between Remote System Upgrade Circuitry

and FPGA Logic Array

The dedicated remote system upgrade circuitry drives (or receives) seven

signals to (or from) the FPGA logic array. The FPGA logic array uses these

signals to read and write the remote system upgrade control, status, and

update registers using the remote system upgrade shift register. Table 8–8

lists each of these seven signals and describes their functionality.

Except for RU_nRSTIMER and RU_CAPTnUPDT, the logic array signals are

enabled for both remote and local update modes and for both factory and

application configurations. RU_nRSTIMER is only valid for application

configurations in remote update mode, since local update configurations

and factory configurations have the user watchdog timer disabled. When

RU_CAPTnUPDT

is low, the device can write to the update register only

for factory configurations in remote update mode, since this is the only

case where the update register is written to by the user logic. When the

signal goes high, the contents of the update register are

written into the control register for controlling the next configuration

Table 8–8. Interface Signals between Remote System Upgrade Circuitry and FPGA Logic Array (Part 1

Signal Name

Signal Direction

Description

Input to remote system

upgrade block (driven by

FPGA logic array)

Request from the application configuration to reset the user

watchdog timer with its initial count. A falling edge of this signal

triggers a reset of the user watchdog timer.

Input to remote system

upgrade block (driven by

FPGA logic array)

When driven low, this signal triggers the device to reconfigure.

If asserted by the factory configuration in remote update

mode, the application configuration specified in the remote

update control register is loaded. If requested by the

application configuration in remote update mode, the factory

configuration is loaded.

In the local updated mode, the application configuration is

loaded whenever this signal is asserted.

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