參數(shù)資料
型號(hào)： FW322
英文描述： 1394A PCI PHY/Link Open Host Controller Interface
中文描述： 1394A端口物理層的PCI /鏈接開放主機(jī)控制器接口
文件頁(yè)數(shù)： 16/148頁(yè)
文件大?。?/td> 1723K
代理商： FW322
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16
Lucent Technologies Inc.
FW322
1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
February 2001
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
Pin
100
Symbol*
TPB0
–
* Active-low signals within this document are indicated by an N following the symbol names.
Type
Description
Analog I/O
Port 0, Port Cable Pair B.
TPB0± is the port B connec-
tion to the twisted-pair cable. Board traces from each
pair of positive and negative differential signal pins
should be kept matched and as short as possible to the
external load resistors and to the cable connector.
Port 0, Port Cable Pair A.
TPA0± is the port A connec-
tion to the twisted-pair cable. Board traces from each
pair of positive and negative differential signal pins
should be kept matched and as short as possible to the
external load resistors and to the cable connector.
Port 0, Twisted-Pair Bias.
TPBIAS0 provides the
1.86 V nominal bias voltage needed for proper opera-
tion of the twisted-pair cable drivers and receivers and
for sending a valid cable connection signal to the
remote nodes.
Analog Circuit Ground.
All V
SSA
signals should be
tied together to a low-impedance ground plane.
Analog Circuit Power.
V
DDA
supplies power to the
analog portion of the device.
Current Setting Resistor.
An internal reference
voltage is applied to a resistor connected between R0
and R1 to set the operating current and the cable driver
output current. A low temperature-coefficient resistor
(TCR) with a value of 2.49 k
± 1% should be used to
meet the
IEEE
1394-1995 standard requirements for
output voltage limits.
Power for PLL Circuit.
PLLV
DD
supplies power to the
PLL circuitry portion of the device.
Ground for PLL Circuit.
PLLV
SS
is tied to a low-imped-
ance ground plane.
Crystal Oscillator.
XI and XO connect to a
24.576 MHz parallel resonant fundamental mode
crystal. Although when a 24.576 MHz clock source is
used, it can be connected to XI with XO left uncon-
nected. The optimum values for the external shunt
capacitors are dependent on the specifications of the
crystal used. The suggested values of 12 pF are appro-
priate for crystal with 7 pF specified loads. For more
details, see the Crystal Selection Considerations
section.
101
TPB0+
102
TPA0
–
Analog I/O
103
TPA0+
104
TPBIAS0
Analog I/O
105
V
SSA
—
106
V
DDA
—
107
R0
I
108
R1
109
PLLV
DD
—
110
PLLV
SS
—
111
XI
—
112
XO
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