Lucent Technologies Inc.
17
Data Sheet, Rev. 1
February 2001
FW322
1394A PCI PHY/Link Open Host Controller Interface
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
Application Schematic
The application schematic presents a complete two-port, 400 Mbits/s
IEEE
1394a-2000 design, featuring the
Lucent FW322 PCI bus-based host OHCI controller and 400 Mbits/s PHY core. The FW322 device needs only a
power source (U3), connection to PCI interface, 1394a-2000 terminators and connectors, crystal, and serial
EEPROM. No external PHY is required because the FW322 contains both host controller and PHY core functions.
This design is a secondary (Class 4) power provider to the 1394 bus, and will participate in the required 1394a-
2000 bus activities, even when power on the PCI bus is not energized.
Pin
113
Symbol*
RESETN
* Active-low signals within this document are indicated by an N following the symbol names.
Type
I
Description
Reset (Active-Low).
When RESETN is asserted low
(active), a bus reset condition is set on the active cable
ports and the internal PHY core logic is reset to the
reset start state. An internal pull-up resistor, which is
connected to V
DD
, is provided, so only an external delay
capacitor and resistor are required. This input is a stan-
dard logic buffer and can also be driven by an open-
drain logic output buffer.
Test.
Used for device testing. Tie to V
SS
.
Test Mode Control.
SM is used during the manufac-
turing test and should be tied to V
SS
.
Test Mode Control.
SE is used during the manufac-
turing test and should be tied to V
SS
.
No Connect.
No Connect.
Power.
CardBusN.
Selects mode of operation for PCI output
buffers. Tie low for cardbus operation, high for PCI
operation. An internal pull-up is provided to force
buffers to PCI mode, if no connection is made to this
pin.
114
115
PTEST
SM
I
I
116
SE
I
117
118
119
120
NC
NC
V
DD
—
—
—
I
CARDBUSN