參數(shù)資料
型號(hào)： GS8182S18BD-250I
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 1M X 18 DDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, FPBGA-165
文件頁(yè)數(shù)： 13/37頁(yè)
文件大?。?/td> 564K
代理商： GS8182S18BD-250I
GS8182S08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03b 6/2010
20/37
2007, GSI Technology
Hold Times
Address Input Hold Time
tKHAX
0.4
—
0.4
—
0.4
—
0.4
—
0.5
—
0.6
—
0.7
—
ns
1
Control Input Hold Time (RW, LD)
tKHIX
0.4
—
0.4
—
0.4
—
0.4
—
0.5
—
0.6
—
0.7
—
ns
2
Control Input Hold Time (BWX,
NWX)
tIVKH
0.28
—
0.28
—
0.28
—
0.3
—
0.35
—
0.4
—
0.5
—
ns
3
Data Input Hold Time
tKHDX
0.28
—
0.28
—
0.28
—
0.3
—
0.35
—
0.4
—
0.5
—
ns
Notes:
1.
All Address inputs must meet the specified setup and hold times for all latching clock edges.
2.
Control singles are RW, LD.
3.
Control singles BW0, BW1, (NW0, NW1 for x8) and BW2, BW3 for x36.
4.
If C, C are tied high, K, K become the references for C, C timing parameters.
5.
To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter
that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same
board to be at such different voltages and temperatures.
6.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
7.
VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
8.
Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands
and test setup variations.
AC Electrical Characteristics (Continued)
Parameter
Symbol
-400
-375
-333
-300
-250
-200
-167
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
相關(guān)PDF資料
PDF描述
GS8182S18BD-300I 1M X 18 DDR SRAM, 0.45 ns, PBGA165
GS8182T08GBD-167IT 2M X 8 DDR SRAM, 0.5 ns, PBGA165
GS82032AT-4I 64K X 32 CACHE SRAM, 10 ns, PQFP100
GS8342S36AE-200S 1M X 36 DDR SRAM, 0.45 ns, PBGA165
GS880Z18CT-250IVT 512K X 18 ZBT SRAM, QFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8182S18D-250 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 1MX18 0.45NS 165FBGA - Trays
GS8182S18D-250I 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 1MX18 0.45NS 165FPBGA - Trays
GS8182S36BD-167 制造商:GSI Technology 功能描述:512K X 36 (18 MEG) BURST OF 2 - Trays
GS8182S36BD-167I 制造商:GSI Technology 功能描述:512K X 36 (18 MEG) BURST OF 2 - Trays
GS8182S36BD-200 制造商:GSI Technology 功能描述:512K X 36 (18 MEG) BURST OF 2 - Trays
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