參數(shù)資料
型號(hào): GT-48212
廠商: Galileo Technology Services, LLC
英文描述: Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級(jí)交換式 10+10/100 BaseX以太網(wǎng)控制器)
中文描述: 先進(jìn)的交換式以太網(wǎng)控制器的10 10/100 BaseX(高級(jí)交換式10 10/100 BaseX以太網(wǎng)控制器)
文件頁(yè)數(shù): 52/135頁(yè)
文件大?。?/td> 1619K
代理商: GT-48212
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GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
GALI
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TECHNOLOGY
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Revision 1.2
23
5.
BUFFERS AND QUEUES
The GT-482xx incorporates 30 transmit queues for the 12 or 8 Ethernet ports, two Fast Ethernet ports and the
CPU bus port. In each port there are two queues, one for high and one for low priority. The GT-482xx also con-
tains a common receive buffer area. The receive buffers are allocated to the receive ports and the CPU. The GT-
482xx incorporates a simple mechanism to prevent head-of-line blocking (See Section 5.2 "Head-of-Line Block-
ing" on page 25). The receive buffers as well as the transmit queues are located in the DRAM with the Address
Table. See Table 4 on page 24 for DRAM address mapping in the GT-482xx.
The GT-482xx data structure has the following components:
Receive Buffer - A common Receive Buffer area for all ports. The buffer is divided into 512 or 2048
blocks (depending on the DRAM size) of 1.5KBytes (1536 bytes) each. Each block contains the entire
packet.
Rx Empty List - A list of 512 or 2048 bits. Each bit contains the status of its appropriate receive block in
the DRAM (empty or occupied).
Tx Descriptors - A set of 30 transmit descriptor rings. Each ring contains 512 or 2048 descriptors. The
descriptor size is one 32-bit word and contains the Block Address divided by 0x600 (1.5K), the byte count
and the packet type (Multicast or Unicast).
Read/Write Pointers - 30 pairs of pointers to the transmit descriptors.
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