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| 型號(hào)： | GT-48212 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級(jí)交換式 10+10/100 BaseX以太網(wǎng)控制器) |
| 中文描述： | 先進(jìn)的交換式以太網(wǎng)控制器的10 10/100 BaseX（高級(jí)交換式10 10/100 BaseX以太網(wǎng)控制器） |
| 文件頁(yè)數(shù)： | 68/135頁(yè) |
| 文件大?。?/td> | 1619K |
| 代理商： | GT-48212 |
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GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
GALI
LEO
TECHNOLOGY
CONFI
D
ENTI
AL
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DO
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REPRODUCE
38
Revision 1.2
8.3.2
Enabled Auto-Negotiation
When DData[27:26] are HIGH at reset, Auto-Negotiation is enabled for each port. The GT-482xx decodes the
duplex mode for each port from the values of the Auto-Negotiation Advertisement register and the Auto-Negotia-
tion Link Partner Ability registers at the end of the Auto-Negotiation process. Once the duplex mode is resolved,
the GT-482xx updates the Port Control registers with that duplex mode. The GT-482xx continuously performs the
following operations for each port (PHY addresses 1 and 2 alternately), implemented as READ commands issued
via the MDC/MDIO interface:
1.
Reads the PHY Auto-Negotiation Complete status. When PHY bit 1.5 (Register 1, bit 5) is '0' switches to
half-duplex mode and continues to read PHY register bit 1.5. When PHY bit 1.5 is '1', signaling Auto-
Negotiation is complete and step two is performed.
Notes:
Steps 2 through 6 are performed once every time the PHY bit 1.5 transitions from '0' to '1'. Once PHY bit
1.5 remains '1' and PHY registers 4 and 5 are read, the GT-482xx continues to read PHY register 1, and
monitors PHY bit 1.5. Steps 2 to 6 are performed once, if after Rst* de-assertion, the PHY bit 1.5 is read
as '1', to update the GT-482xx duplex mode.
PHY bit 1.2 (Link Status) is read and latched during this register read operation, regardless of the Auto-
Negotiation status.
2.
Reads the Auto-Negotiation Advertisement register, PHY Register 4 and continues to step 3.
3.
Reads the Auto-Negotiation Link Partner Ability register, PHY Register 5 and continues to step 4.
4.
Resolves the highest common ability of the two link partners as follows (according to the 802.3u Priority
Resolution clause 28B.3):
if (bit 4.8 AND bit 5.8) == '1' then ability is 100BASE-TX full duplex
else if (bit 4.9 AND bit 5.9) == '1' then ability is 100BASE-T4 half duplex
else if (bit 4.7 AND bit 5.7) == '1' then ability is 100BASE-TX half duplex
else if (bit 4.6 AND bit 5.6) == '1' then ability is 10BASE-T full duplex
else ability is 10BASE-T half duplex;
Continues to step 5.
5.
Resolves the duplex mode of the two link partners as follows:
if ((ability == "100BASE-TX full duplex") or (ability == "10BASE-T full duplex")) then
duplex mode = FULL DUPLEX
else duplex mode = HALF DUPLEX;
Note: The value of the duplex mode indication changes only after reading both PHY registers 4 and 5.
Continues to step 6.
6.
Updates the Port Control register by writing the correct duplex mode bit.
8.4
Backoff Algorithm Options
The GT-482xx implements the truncated exponential backoff algorithm defined by the 802.3 standard. Aggres-
siveness of the backoff algorithm used by all of the ports is controlled by the Limit4 pin or bit in the Global control
register. Limit4 controls the number of consecutive packet collisions that occur before the collision counter is reset.
When Limit4 is LOW, the GT-482xx resets the collision counter after 16 consecutive retransmit trials, restarts the
backoff algorithm, and continues to try to retransmit the frame. The retransmission is performed from the data
stored in the DRAM. In the case of a successful transmission, the GT-482xx is ready to transmit any other frames
queued in its transmit FIFO within the minimum IPG of the link.
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